AD6600STSLASHPCB datasheet(3/24 Pages) AD

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REV. 0

–3–

AD6600

TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS1

(AVCC = 5 V, DVCC = 3.3 V; ENC and

ENC = 20 MSPS; T

MIN = –40 C, TMAX = +85 C unless otherwise noted.)

Test

AD6600AST

Parameter

Name

Temp

Level

Min

Typ

Max

Unit

A/D CONVERTER

Conversion Rate

fENC

1/(tENC)

MSPS

Maximum Conversion Rate

Full

MSPS

Minimum Conversion Rate

Full

MSPS

Aperture Uncertainty

°C

0.3

ps rms

ENCODE INPUTS (ENC,

ENC)2

Period

tENC

Full

Pulsewidth High

tENCH

Full

Pulsewidth Low

tENCL

Full

× CLOCK OUTPUT (CLK2×)5

Output Frequency

× fENC

MSPS

Output Period6

tCLK2×_1

Full

tENCL

tCLK2×_2

Full

tENCH

CLK2

× Pulsewidth Low6

tCLK2×L

Full

tENCH/2

Output Risetime7

Full

Output Falltime

Full

2.6

OUTPUT RISE/FALL TIMES8

Output Risetime (D10:D0, RSSI2:0)

Full

Output Falltime (D10:D0, RSSI2:0)

Full

8.4

Output Risetime (AB_OUT)

Full

Output Falltime (AB_OUT)

Full

6.2

NOTES

1See AD6600 Timing Diagrams.

2All switching specifications tested by driving ENC and

ENC differentially.

3Several timing specifications are a function of Encode high time, t

ENCH; these specifications are shown in the data tables and timing diagrams. Encode duty cycle

should be kept as close to 50% as possible.

4Encode pulse low directly affects the amount of settling time available at FLT resonant port. See External Analog (Resonant) Filter section for details.

5The 2

× Clock is generated internally, therefore some specifications are functions of encode period and duty cycle. All timing measurements to or from CLK2 × are

referenced to 2.0 V crossing.

6This specification IS a function of Encode period and duty cycle; reference timing diagrams Figure 8.

7Output rise time is measured from 20% point to 80% point of total CLK2

× voltage swing; output fall time is measured from 80% point to 20% point of total CLK2×

voltage swing.

8Output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% point to 20% point of total data voltage

swing. All outputs specified with 10 pF load.

Specifications subject to change without notice.

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