AD6640STSLASHPCB datasheet(14/24 Pages) AD

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AD6640

–14–

REV. 0

The analog input range of the PCB is

±0.5 volts (i.e., signal ac-

coupled to AD6640).

The encode signal may be generated using an onboard crystal

oscillator, U1. The oscillator is socketed and may be replaced

by an external encode source via J1. If an external source is

used, it should be a high quality TTL source. A transformer

converts the single-ended TTL signal to a differential clock (see

Encoding the AD6640). Since the encode is coupled with a

transformer, a sine wave could have been used; note, however,

that U5 requires TTL levels to function properly.

Table I. AD6640ST/PCB Bill of Material

Item

Quantity

Reference

Description

+5 VA, GND

Banana Jack

C7–C9, C11–C17, C19

Ceramic Chip Capacitor 0805, 0.1

µF

C4, C6

Tantalum Chip Capacitor 10

µF

40-Pin Double Row Male Header

J1, J2, J4

BNC Coaxial PCB Connector

Surface Mount Resistor 1206, 348

Ω

R2–R14, R20–R25, R30–R35

Surface Mount Resistor 1206, 348

Ω

R15

Surface Mount Resistor 1206, 100

Ω

R16

Surface Mount Resistor 1206, 270

Ω

T1, T2

Surface Mount Transformer Mini-Circuits T4–1T, 1:4 Ratio

Clock Oscillator (Optional)

DUT

AD6640AST 12-Bit–65 MSPS ADC Converter

U3, U4

74LCX574 Octal Latch

74LVQ00 Quad Two Input NAND Gate

C1, C18

Ceramic Chip Capacitor 0508, 0.01

µF Low Inductance

C2, C3

Ceramic Chip Capacitor 0508, 0.1

µF Low Inductance

CR1, CR2

1N2810 Schottky Diode

AD6640 output data is latched using 74LCX574 (U3, U4)

latches following 348 ohm series resistors. The resistors limit

the current that would otherwise flow due to the digital output

slew rate. The resistor value was chosen to represent a time

constant of ~25% of the data rate at 65 MHz. This reduces slew

rate while not appreciably distorting the data waveform. Data is

latched in a pipeline configuration; a rising edge generates the

new AD6640 data sample, latches the previous data at the con-

verter output, and strobes the external data register over J3.

NOTE: Power and ground must be applied to J3 to power the

digital logic section of the evaluation board.

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