AD6644

–12–

REV. 0

THEORY OF OPERATION

The AD6644 analog-to-digital converter (ADC) employs a three

stage subrange architecture. This design approach achieves the

required accuracy and speed while maintaining low power and

small die size.

As shown in the functional block diagram, the AD6644 has

complementary analog input pins, AIN and AIN . Each analog

input is centered at 2.4 V and should swing

± 0.55 V around

this reference (Figure 2). Since AIN and AIN are 180 degrees

out of phase, the differential analog input signal is 2.2 V peak-

to-peak.

Both analog inputs are buffered prior to the first track-and-hold,

TH1. The high state of the ENCODE pulse places TH1 in hold

mode. The held value of TH1 is applied to the input of a 5-bit

coarse ADC1. The digital output of ADC1 drives a 5-bit digital-

to-analog converter, DAC1. DAC1 requires 14 bits of precision

which is achieved through laser trimming. The output of DAC1

is subtracted from the delayed analog signal at the input of TH3

to generate a first residue signal. TH2 provides an analog pipe-

line delay to compensate for the digital delay of ADC1.

The first residue signal is applied to a second conversion stage

consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4.

The second DAC requires 10 bits of precision which is met by

the process with no trim. The input to TH5 is a second residue

signal generated by subtracting the quantized output of DAC2

from the first residue signal held by TH4. TH5 drives a final

6-bit ADC3.

The digital outputs from ADC1, ADC2, and ADC3 are added

together and corrected in the digital error correction logic to

generate the final output data. The result is a 14-bit parallel

digital CMOS-compatible word, coded as two's complement.

APPLYING THE AD6644

Encoding the AD6644

The AD6644 encode signal must be a high quality, extremely low

phase noise source to prevent degradation of performance. Main-

taining 14-bit accuracy places a premium on encode clock phase

noise. SNR performance can easily degrade by 3 dB to 4 dB

with 70 MHz input signals when using a high-jitter clock source.

See Analog Devices’ Application Note AN-501, “Aperture Uncer-

tainty and ADC System Performance” for complete details.

For optimum performance, the AD6644 must be clocked

differentially. The encode signal is usually ac-coupled into the

ENCODE and ENCODE pins via a transformer or capacitors.

These pins are biased internally and require no additional bias.

Shown below is one preferred method for clocking the AD6644.

The clock source (low jitter) is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the transformer secondary limit clock excursions

into the AD6644 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to the other portions of the AD6644, and limits the noise

presented to the ENCODE inputs. A crystal clock oscillator can

also be used to drive the RF transformer if an appropriate limiting

resistor (typically 100

Ω) is placed in the series with the primary.

ENCODE

ENCODE

AD6644

T1–4T

HSMS2812

DIODES

CLOCK

SOURCE

0.1 F

100

Figure 25. Crystal Clock Oscillator – Differential Encode

If a low jitter ECL/PECL clock is available, another option is to

ac-couple a differential ECL/PECL signal to the encode input pins

as shown below. A device that offers excellent jitter performance

is the MC100LVEL16 (or same family) from Motorola.

ENCODE

ENCODE

AD6644

0.1 F

0.1 F

VT

VT

ECL/

PECL

Figure 26. Differential ECL for Encode

Analog Input

As with most new high-speed, high dynamic range analog-to-

digital converters, the analog input to the AD6644 is differential.

Differential inputs allow much improvement in performance

on-chip as signals are processed through the analog stages. Most

of the improvement is a result of differential analog stages having

high rejection of even order harmonics. There are also benefits

at the PCB level. First, differential inputs have high common-

mode rejection to stray signals such as ground and power noise.

Also, they provide good rejection to common-mode signals such as

local oscillator feedthrough.

The AD6644 input voltage range is offset from ground by 2.4 V.

Each analog input connects through a 500

Ω resistor to a 2.4 V

bias voltage and to the input of a differential buffer (Figure 2). The

resistor network on the input properly biases the followers for maxi-

mum linearity and range. Therefore, the analog source driving the

AD6644 should be ac-coupled to the input pins. Since the differ-

ential input impedance of the AD6644 is 1 k

Ω, the analog input

power requirement is only –2 dBm, simplifying the driver amplifier

in many cases. To take full advantage of this high-input imped-

ance, a 20:1 transformer would be required. This is a large ratio

and could result in unsatisfactory performance. In this case, a

lower step-up ratio could be used. The recommended method for

driving the analog input of the AD6644 is to use a 4:1 RF trans-

to 25

Ω, along with a 4:1 transformer, the input would match

to a 50

Ω source with a full-scale drive of 4.8 dBm. Series resis-

used to isolate the transformer from A/D. This will limit the

amount of dynamic current from the A/D flowing back into

the secondary of the transformer. The terminating resistor (RT)

should be placed on the primary side of the transformer.

AIN

AIN

AD6644

T1–4T

ANALOG INPUT

SIGNAL

0.1 F

Figure 27. Transformer-Coupled Analog Input Circuit