AD6644

–13–

REV. 0

In applications where dc-coupling is required, a new differential

output op amp from Analog Devices, the AD8138, can be used

to drive the AD6644 (Figure 28). The AD8138 op amp provides

single-ended-to-differential conversion, which reduces overall

system cost and minimizes layout requirements.

AD8138

499

AD6644

25

25

AIN

499

0.1 F

499

499

5V

AIN

DIGITAL

OUTPUTS

Figure 28. DC-Coupled Analog Input Circuit

Power Supplies

Care should be taken when selecting a power source. Linear

supplies are strongly recommended. Switching supplies tend to

have radiated components that may be “received” by the AD6644.

Each of the power supply pins should be decoupled as closely to

the package as possible using 0.1

µF chip capacitors.

The AD6644 has separate digital and analog power supply pins.

power supplies. This is because the fast digital output swings

can couple switching current back into the analog supplies. Note

Output Loading

Care must be taken when designing the data receivers for the

AD6644. It is recommended that the digital outputs drive a

series resistor (e.g. 100

Ω) followed by a gate like 74LCX574.

To minimize capacitive loading, there should only be one gate

on each output pin. An example of this is shown in the evaluation

board schematic shown in Figure 30. The digital outputs of the

AD6644 have a constant output slew rate of 1 V/ns. A typical

CMOS gate combined with a PCB trace will have a load of

approximately 10 pF. Therefore, as each bit switches, 10 mA

(10 pF

1 V

1 ns) of dynamic current per bit will flow in or out

of the device. A full scale transition can cause up to 140 mA

(14 bits

10 mA/bit) of current to flow through the output stages.

The series resistors should be placed as close to the AD6644 as

possible to limit the amount of current that can flow into the out-

put stage. These switching currents are confined between ground

they can appreciably add to the dynamic switching currents of

the AD6644. It should also be noted that extra capacitive loading

will increase output timing and invalidate timing specifications.

Digital output timing is guaranteed with 10 pF loads.

Layout Information

The schematic of the evaluation board (Figure 30) represents a

typical implementation of the AD6644. A multilayer board is

recommended to achieve the best results. It is highly recom-

mended that high-quality, ceramic chip capacitors be used to

decouple each supply pin to ground directly at the device. The

pinout of the AD6644 facilitates ease of use in the implementa-

tion of high frequency, high resolution design practices. All of

the digital outputs are segregated to two sides of the chip, with

the inputs on the opposite side for isolation purposes.

Care should be taken when routing the digital output traces.

To prevent coupling through the digital outputs into the analog

portion of the AD6644, minimal capacitive loading should be

placed on these outputs. It is recommended that a fan-out of

only one gate be used for all AD6644 digital outputs.

The layout of the Encode circuit is equally critical. Any noise

received on this circuitry will result in corruption in the digi-

tization process and lower overall performance. The Encode clock

must be isolated from the digital outputs and the analog inputs.

Jitter Considerations

The signal-to-noise ratio (SNR) for an ADC can be predicted.

When normalized to ADC codes, Equation 1 accurately predicts

the SNR based on three terms. These are jitter, average DNL

error, and thermal noise. Each of these terms contributes to the

noise within the converter.

SNR

f

t

V

N

ANALOG

RMS

NOISE RMS

N

=×

+











 +× ×

×

+

























–

log

()

()

/

20

1

2

2

2

2

2

2

12

ε

π

J

(1)

= analog input frequency.

= rms jitter of the encode (rms sum of encode

source and internal encode circuitry).

ε

= average DNL of the ADC (typically 0.41 LSB).

N

= Number of bits in the ADC.

of the ADC (typically 2.5 LSB).

For a 14-bit analog-to-digital converter like the AD6644, aper-

ture jitter can greatly affect the SNR performance as the analog

frequency is increased. The chart below shows a family of curves

that demonstrates the expected SNR performance of the AD6644

as jitter increases. The chart is derived from the above equation.

For a complete discussion of aperture jitter, please consult

Analog Devices’ Application Note AN-501, “Aperture

Uncertainty and ADC System Performance.”

JITTER – ps

0

0.1

55

0.2

0.3

0.4

0.5

0.6

60

65

70

75

80

AIN = 190MHz

AIN = 150MHz

AIN = 110MHz

AIN = 30MHz

AIN = 70MHz

Figure 29. SNR vs. Jitter