AD7476SRT-R2 datasheet(5/20 Pages) AD

5 / 20 page

REV. D

AD7476/AD7477/AD7478

–5–

TIMING SPECIFICATIONS1, 2 (V

DD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)

Limit at TMIN, TMAX

AD7476/AD7477/AD7478

Parameter

3 V

Unit

Description

fSCLK

kHz min

MHz max

A Version

MHz max

B Version

tCONVERT

× tSCLK

tQUIET

ns min

Minimum Quiet Time Required between Bus Relinquish and

Start of Next Conversion

ns min

Minimum

CS Pulsewidth

ns min

CS to SCLK Setup Time

ns max

Delay from

CS until SDATA Three-State Disabled

ns max

Data Access Time after SCLK Falling Edge, A Version

ns max

Data Access Time after SCLK Falling Edge, B Version

0.4

× t

SCLK

0.4

× t

SCLK

ns min

SCLK Low Pulsewidth

0.4

× tSCLK

0.4

× tSCLK

ns min

SCLK High Pulsewidth

ns min

SCLK to Data Valid Hold Time

ns min

SCLK Falling Edge to SDATA High Impedance

ns max

SCLK Falling Edge to SDATA High Impedance

tPOWER-UP

µs typ

Power-Up Time from Full Power-Down

NOTES

1Guaranteed by characterization. All input signals are speciﬁed with tr = tf = 5 ns (10% to 90% of V

DD) and timed from a voltage level of 1.6 V.

2A Version timing specifications apply to the AD7477 S Version and AD7478 S Version; B Version timing specifications apply to the AD7476 S Version.

33 V specifications apply from V

DD = 2.7 V to 3.6 V for A Version; 3 V specifications apply from V DD = 2.35 V to 3.6 V for B Version; 5 V specifications apply from

VDD = 4.75 V to 5.25 V.

4Mark/Space ratio for the SCLK input is 40/60 to 60/40.

5Measured with the load circuit of Figure 1 and deﬁned as the time required for the output to cross 0.8 V or 2.0 V.

8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish time

of the part and is independent of the bus loading.

7See Power-Up Time section.

Speciﬁcations subject to change without notice.

200 A

IOL

200 A

IOH

50pF

TO OUTPUT

1.6V

Figure 1. Load Circuit for Digital Output Timing

Speciﬁcations

AD7476SRT-R2 数据表(PDF) 5 Page - Analog Devices

AD7476SRT-R2 数据表(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载

链接网址

AD7476SRT-R2 数据表(PDF) 5 Page - Analog Devices

AD7476SRT-R2 数据表(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表 下载

链接网址

数据表下载