REV. 0

–26–

AD7708/AD7718

Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On-Reset = 00Hex)

The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-

tions Register selecting the next operation to be a read and load Bits A3-A0 with 0, 0, 0,0. Table XIV outlines the bit designations

for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the

first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.

R

S7

6

R

S5

R

S4

R

S3

R

S2

R

S1

R

S0

R

S

Y

D

R)

0

()

0

(

0)

0

(

L

A

C)

0

(

0)

0

(

R

R

E)

0

(

0)

0

(

0)

0

(

K

C

O

L

Table XIV. Status Register Bit Designations

Bit

Bit

Location

Mnemonic Description

SR7

RDY

Ready Bit for the ADC

Set when data is transferred to the ADC data registers or on completion of calibration cycle. The RDY

bit is cleared automatically a period of time before the data register is updated with a new conversion

result or after the ADC data register has been read. This bit is also cleared by a write to the mode bits to

indicate a conversion or calibration. The

RDY pin is the complement of the RDY bit.

SR6

0

Bit is automatically cleared. Reserved for future use

SR5

CAL

Calibration Status Bit

Set to indicate completion of calibration. It is set at the same time that the RDY is set high.

Cleared by a write to the mode bits to start another ADC conversion or calibration.

SR4

0

This bit is automatically cleared. Reserved for future use

SR3

ERR

ADC Error Bit

Set to indicate that the result written to the ADC data register has been clamped to all zeros or all ones.

After a calibration this bit also flags error conditions that caused the calibration registers not to be

written. Error sources include Overrange.

Cleared by a write to the mode bits to initiate a conversion or calibration.

SR2

0

This bit is automatically cleared. Reserved for future use

SR1

0

This bit is automatically cleared. Reserved for future use

SR0

LOCK

PLL Lock Status Bit.

Set if the PLL has locked onto the 32.768 kHz crystal oscillator clock. If the user is worried about

exact sampling frequencies etc., the LOCK bit should be interrogated and the result discarded if the

LOCK bit is zero.