REV. A

AD7819

–4–

PIN FUNCTION DESCRIPTIONS

Pin

No.

Mnemonic

Description

3

GND

Analog and Digital Ground.

4

CONVST

Convert Start. A low-to-high transition on this pin initiates a 1

µs pulse on an internally generated

CONVST signal. A high-to-low transition on this line initiates the conversion process if the internal

CONVST signal is low. Depending on the signal on this pin at the end of a conversion, the AD7819

automatically powers down.

5

CS

Chip Select. This is a logic input.

CS is used in conjunction with RD to enable outputs.

6

RD

Read Pin. This is a logic input. When

CS is low and RD goes low, the DB7–DB0 leave their high

impedance state and data is driven onto the data bus.

7

BUSY

ADC Busy Signal. This is a logic output. This signal goes logic high during the conversion process.

8–15

DB0–DB7

Data Bit 0 to 7. These outputs are three-state TTL-compatible.

16

Positive power supply voltage, +2.7 V to +5.5 V.

PIN CONFIGURATION

DIP/SOIC

14

13

12

11

15

10

9

16

8

1

2

3

4

7

6

5

TOP VIEW

(Not to Scale)

AD7819

DB5

DB6

DB7

GND

CONVST

DB2

DB3

DB4

CS

RD

BUSY

DB0

DB1