REV. A

AD7819

–8–

Typical Performance Characteristics

THROUGHPUT – kSPS

10

1

0.01

050

5

1015

20

25

30

35

4045

0.1

Figure 10. Power vs. Throughput

0

–60

–100

–10

–50

–70

–90

–30

–40

–80

–20

FREQUENCY – kHz

066

7

13202733

40

47

5360

AD7819

2048 POINT FFT

SAMPLING 136.054kHz

FIN 29.961kHz

Figure 11. SNR

TIMING AND CONTROL

The AD7819 has only one input for timing and control, i.e.,

the

CONVST (convert start signal). The rising edge of this

CONVST signal initiates a 1

µs pulse on an internally generated

CONVST signal. This pulse is present to ensure the part has

enough time to power up before a conversion is initiated. If the

external

CONVST signal is low, the falling edge of the inter-

nal

CONVST signal will cause the sampling circuit to go into

hold mode and initiate a conversion. If, however, the external

CONVST signal is high when the internal CONVST goes low,

it is upon the falling edge of the external

CONVST signal that

the sampling circuitry will go into hold mode and initiate a

conversion. The use of the internally generated 1

µs pulse as

previously described can be likened to the configuration shown

in Figure 12. The application of a

CONVST signal at the

CONVST pin triggers the generation of a 1

µs pulse. Both the

external

CONVST and this internal CONVST are input to an

OR gate. The resultant signal has the duration of the longer of

the two input signals. Once a conversion has been initiated, the

BUSY signal goes high to indicate a conversion is in progress. At

the end of conversion the sampling circuit returns to its track-

ing mode. The end of conversion is indicated by the

BUSY

signal going low. This signal may be used to initiate an ISR on a

microprocessor. At this point the conversion result is latched

into the output register where it may be read. The AD7819 has

an 8-bit wide parallel interface. The state of the external

CONVST

signal at the end of conversion also establishes the mode of

operation of the AD7819.

Mode 1 Operation (High Speed Sampling)

If the external

CONVST is logic high when BUSY goes low, the

part is said to be in Mode 1 operation. While operating in Mode

1 the AD7819 will not power down between conversions. The

AD7819 should be operated in Mode 1 for high speed sam-

pling applications, i.e., throughputs greater than 100 kSPS.

Figure 13 shows the timing for Mode 1 operation. From this

diagram one can see that a minimum delay of the sum of the

conversion time and read time must be left between two succes-

sive falling edges of the external

CONVST. This is to ensure that

a conversion is not initiated during a read.

Mode 2 Operation (Automatic Power-Down)

At slower throughput rates the AD7819 may be powered down

between conversion to give a superior power performance.

This is Mode 2 Operation and it is achieved by bringing the

CONVST signal logic low before the falling edge of BUSY. Fig-

ure 14 shows the timing for Mode 2 Operation. The falling edge

of the external

CONVST signal may occur before or after the

falling edge of the internal

CONVST signal, but it is the later

occurring falling edge of both that controls when the first conver-

sion will take place. If the falling edge of the external

CONVST

occurs after that of the internal

CONVST, it means that the

moment of the first conversion is controlled exactly, regardless

of any jitter associated with the internal

CONVST signal. The

parallel interface is still fully operational while the AD7819 is

powered down. The AD7819 is powered up again on the rising

edge of the

CONVST signal. The gated CONVST pulse will

now remain high long enough for the AD7819 to fully power

up, which takes about 1

µs. This is ensured by the internal

CONVST signal, which will remain high for 1

µs.

1 s

EXT

INT

CONVST

(PIN 4)

GATED

Figure 12.