TS7001 datasheet(3/20 Pages) TOUCHSTONE

3 / 20 page

TS7001

TS7001DS r1p0

Page 3

RTFDS

ELECTRICAL CHARACTERISTICS

VDD = +2.7V to +3.6V; VREF = 2.5V External/internal reference unless otherwise noted; fSCLK = 3 MHz;

TA = TMIN to TMAX, unless otherwise noted.

Parameter

Limit

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal to Noise + Distortion Ratio (SNR)

dB (typ)

fIN = 10 kHz sine wave, fSAMPLE = 187.5ksps

Total Harmonic Distortion (THD)

−80

dB (typ)

fIN = 10 kHz sine wave, fSAMPLE = 187.5ksps

Peak Harmonic or Spurious Noise

−80

db (typ)

fIN = 10 kHz sine wave, fSAMPLE = 187.5ksps

Intermodulation Distortion (IMD)

Second-Order Terms

−80

dB (typ)

f1 = 9.983 kHz, f2 = 10.05 kHz, fSAMPLE = 187.5ksps

Third-Order Terms

−80

dB (typ)

f1 = 9.983 kHz, f2 = 10.05 kHz, fSAMPLE = 187.5ksps

Channel-to-Channel Isolation

−80

dB (typ)

fIN = 25 kHz

Full-Power Bandwidth

MHz (typ)

Measured at 3 dB down

DC ACCURACY(Any channel)

Resolution

Bits

Integral Nonlinearity

±1

LSB (max)

VDD = 3V

Differential Nonlinearity

±1

LSB (max)

VDD = 3V; Guaranteed no missing codes to 11 bits

Offset Error

±4

LSB (max)

VDD = 3V, dual-channel mode

±6

LSB (typ)

Single-channel mode

Offset Error Match

0.5

LSB (max)

Gain Error

±2

LSB (typ)

Dual-channel mode

±1

LSB (max)

Single-channel mode, external reference

±6

LSB (typ)

Single-channel mode, internal reference

Gain Error Match

LSB (max)

ANALOG INPUT

Input Voltage Range

0 to VREF

Single-channel operation

0 to VDD

Dual-channel operation

Leakage Current

±5

μA (max)

Input Capacitance

pF (typ)

REFERENCE INPUT/OUTPUT

REFIN Input Voltage Range

2.5/VDD

V (min/max)

Single-channel/Dual-channel; Functional from 1.2V

Input Impedance

kΩ (typ)

Very high impedance if internal reference is disabled

REFOUT Output Voltage

2.488/2.513

V (min/max)

Initial accuracy = 0.5%

REFOUT Temperature Coefficient

ppm/°C (typ)

LOGIC INPUTS

Input High Voltage, VINH

2.1

V (min)

VDD = 2.7V to 3.6V

Input Low Voltage, VINL

0.8

V (max)

VDD = 2.7V to 3.6V

Input Current, IIN

±1

μA (max)

Typically 10nA, VIN = 0V or VDD

Input Capacitance, CIN

pF (max)

LOGIC OUTPUTS

Output High Voltage, VOH

VDD − 0.5

V (min)

VDD = 2.7V to 3.6V, ISOURCE = 200 μA

Output Low Voltage, VOL

0.4

V (max)

ISINK = 200 μA

Floating-State Leakage Current

±1

μA (max)

Floating-State Output Capacitance

pF (max)

Output Coding

Straight

(Natural)

Binary

CONVERSION RATE

Throughput Time

SCLK cycles

Conversion time plus acquisition time is 187.5ksps,

with 3 MHz Clock

Track-and-Hold Acquisition Time

1.5

SCLK cycles

Conversion Time

14.5

SCLK cycles

4.833

μs (3 MHz Clock)

TS7001 数据表(PDF) 3 Page - Touchstone Semiconductor Inc

TS7001 数据表(HTML) 3 Page - Touchstone Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载

链接网址

TS7001 数据表(PDF) 3 Page - Touchstone Semiconductor Inc

TS7001 数据表(HTML) 3 Page - Touchstone Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表 下载

链接网址

数据表下载