TS7001 datasheet(13/20 Pages) TOUCHSTONE

13 / 20 page

TS7001

TS7001DS r1p0

Page 13

RTFDS

the supplies by the ADC is commensurately reduced

the longer the TS7001 remains in a powered-down

state.

For

example,

consider

the

following

TS7001

application configuration: (a) the ADC is powered

from VDD = 3V and is configured for PM Mode 3

(that is, [PM1, PM0] = [1,0], where the ADC’s

internal

reference

enabled

and

the

ADC

automatically powers down after the conversion is

completed);

and

(b)

the ADC

operates

throughput rate of 10 ksps with a 3-MHz SCLK.

Given the above configuration, the TS7001

’s power

consumption during normal operation is 2.1mW at

VDD = 3 V (0.7mA x 3V). Since its power-up delay

time is 5

μs and its conversion-plus-acquisition time

is ~5.2

μs (t

CONVERT + tACQ = 14.5 x tSCLK + 1.5 x tSCLK

= 15.5 x tSCLK), the TS7001 consumes 3.5mW for

10.2

μs during each conversion cycle. Since the

conversion cycle time

(100μs) is the reciprocal of the

ADC’s throughput rate (10ksps), the average power

consumed by the TS7001 during each conversion

cycle is (10.2/100) × (2.1mW), or 214.2

μW. The

TS7001

’s power consumption vs. throughput rate

when

configured

for

automatic

shutdown

post

conversion and operating on a 3V supply is

illustrated in Figure 8.

Power Management Operating Modes

Designed to provide flexible power consumption

profiles, the TS7001 incorporates four different

operating modes to optimize

the ADC’s power

consumption/throughput-rate ratio. As previously

described in Table 6, the four different modes of

operation in the TS7001 are controlled by the PM1

and

PM0 bits

the

Control

Also

mentioned

previously,

the

TS7001

can

configured as a read-only ADC by forcing an all

zeros (“0”s) condition in the control register. This can

be easily done by applying a logic LOW at all times

to the DIN pin or hard-wiring the DIN pin directly to

GND.

Power Management Mode 1 Operation:

[PM1,PM0] = [0,0]

Power Management Operating Mode 1 is used to

control the TS7001

’s power-down using the CS pin.

Whenever the

CS pin is low, the TS7001 is fully

powered up; whenever the

CS pin is high, the

TS7001 is completely powered down. When the

pin is toggled high-to-low, all internal circuitry starts

to power up where it can take as long as

5μs for the

TS7001

’s internal circuitry to power up completely.

As a result, any conversion start sequence should

not be initiated during this initial

5μs power-up delay.

Figure 9 shows a general operating diagram of the

TS7001 in PM Mode 1. The analog input signal is

sampled on the second low-to-high SCLK transition

following the initial high-to-low

CS transition. System

timing design should incorporate a 5-

μs delay

between the high-to-low

CS transition and the

second

low-to-high

SCLK

transition.

microcontroller applications, this is achieved by

Figure 9:

TS7001’s Power Management Mode 1 Operation Diagram.

TS7001 数据表(PDF) 13 Page - Touchstone Semiconductor Inc

TS7001 数据表(HTML) 13 Page - Touchstone Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载

链接网址

TS7001 数据表(PDF) 13 Page - Touchstone Semiconductor Inc

TS7001 数据表(HTML) 13 Page - Touchstone Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表 下载

链接网址

数据表下载