AD8320

–4–

REV. 0

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD8320 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model

Temperature Range

Package Description

JA

Package Option

AD8320ARP

–40

°C to +85°C

20-Lead Thermally Enhanced Power SOIC*

53

°C/W

RP-20

AD8320-EB

Evaluation Board

*Shipped in tubes (38 pieces/tube) and dry packed per J-STD-020.

ABSOLUTE MAXIMUM RATINGS*

Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . –0.8 V to +13 V

Input Voltages

Pins 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±3 V

Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5 V

Internal Power Dissipation

Small Outline (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W

Operating Temperature Range . . . . . . . . . . . –40

°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature, Soldering 60 seconds . . . . . . . . . . +300

°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

AD8320

VOUT

VCC

VCC

CLK

DATEN

GND

VCC

PD

VOCM

GND

GND

VIN

VREF

VCC

BYP

GND

GND

SDATA

VCC

GND

PIN FUNCTION DESCRIPTIONS

Pin

Function

Description

1

SDATA

Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal

register with the MSB (most significant bit) first.

2

CLK

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave

register. A Logic 0 to 1 transition latches the data bit and a 1 to 0 transfers the data bit to the slave.

This requires the input serial data word to be valid at or before this clock transition.

3

DATEN

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0 to 1

transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhib-

its serial data transfer into the register. A 1 to 0 transition inhibits the data latch (holds the previous

gain state) and simultaneously enables the register for serial data load.

4, 11, 12,

13, 15, 16

GND

Common External Ground Reference.

5

VOCM

VCC/2 Reference Pin. A dc output reference level that is equal to 1/2 of the supply voltage (VCC).

This port should be externally ac decoupled (0.1

µF cap).

6

PD

Power-Down Low Logic Input. A Logic 0 powers down (shuts off) the power amplifier disabling the

output signal and enabling the reverse amplifier. A Logic 1 enables the output power amplifier and

disables the reverse amplifier.

7, 8, 9, 17, 20 VCC

Common Positive External Supply Voltage.

10

VOUT

Output Signal Port. DC biased to approximately VCC/2.

14

BYP

Internal Bypass. This pin must be externally ac decoupled (0.1

µF cap).

18

VREF

Input Reference Voltage (typically 1.9 V at 27

°C). This port should be externally ac decoupled

(0.1

µF cap).

19

VIN

Analog Voltage Input Signal Port. DC biased to VREF voltage.

WARNING!

ESD SENSITIVE DEVICE