AD9708

–7–

REV. B

FUNCTIONAL DESCRIPTION

Figure 12 shows a simplified block diagram of the AD9708. The

AD9708 consists of a large PMOS current source array capable of

providing up to 20 mA of total current. The array is divided into

31 equal currents that make up the five most significant bits

(MSBs). The remaining 3 LSBs are also implemented with equally

weighted current sources whose sum total equals 7/8th of an

MSB current source. Implementing the upper and lower bits

with current sources helps maintain the DAC’s high output

impedance (i.e. > 100 k

Ω). All of these current sources are

switched to one or the other of the two output nodes (i.e., IOUTA

or IOUTB) via PMOS differential current switches. The switches

are based on a new architecture that drastically improves

distortion performance.

The analog and digital sections of the AD9708 have separate

power supply inputs (i.e., AVDD and DVDD) that can operate

independently over a 2.7 volt to 5.5 volt range. The digital section,

which is capable of operating up to a 125 MSPS clock rate,

consists of edge-triggered latches and segment decoding logic

circuitry. The analog section includes the PMOS current

sources, the associated differential switches, a 1.20 V bandgap

voltage reference and a reference control amplifier.

The full-scale output current is regulated by the reference con-

trol amplifier and can be set from 2 mA to 20 mA via an exter-

both the reference control amplifier and voltage reference

the segmented current sources with the proper scaling factor.

DAC TRANSFER FUNCTION

The AD9708 provides complementary current outputs, IOUTA

and IOUTB. IOUTA will provide a near full-scale current output,

IOUTB, the complementary output, provides no current. The

current output appearing at IOUTA and IOUTB are a function

× I

OUTFS

(1)

× I

OUTFS

(2)

where DAC CODE = 0 to 255 (i.e., Decimal Representation).

× I

REF

(3)

where

(4)

The two current outputs will typically drive a resistive load

directly. If dc coupling is required, IOUTA and IOUTB should

sent the equivalent load resistance seen by IOUTA or IOUTB

as would be the case in a doubly terminated 50

Ω or 75 Ω cable.

The single-ended voltage output appearing at the IOUTA and

IOUTB nodes is simply:

× R

LOAD

(5)

× R

LOAD

(6)

the specified output compliance range to maintain specified

distortion and linearity performance.

IOUTB is:

× R

LOAD

(7)

expressed as:

× (32 R

× V

REFIO

(8)

VOLTAGE REFERENCE AND CONTROL AMPLIFIER

The AD9708 contains an internal 1.20 V bandgap reference

that can be easily disabled and overridden by an external refer-

ence. REFIO serves as either an input or output depending on

whether the internal or an external reference is selected. If

REFLO is tied to ACOM, as shown in Figure 13, the internal

reference is activated and REFIO provides a 1.20 V output. In

this case, the internal reference must be compensated externally

with a ceramic chip capacitor of 0.1

µF or greater from REFIO

to REFLO. Note that REFIO is not designed to drive any ex-

ternal load. It should be buffered with an external amplifier

having an input bias current less than 100 nA if any additional

loading is required.

+1.20V REF

REFLO

REFIO

FS ADJ

50pF

COMP1

0.1 F

CURRENT

SOURCE

ARRAY

+5V

AVDD

SEGMENTED

SWITCHES

LATCHES

DVDD

DCOM

CLOCK

SLEEP

IOUTA

IOUTB

COMP2

ACOM

0.1 F

+5V

2k

0.1 F

AD9708

50

50

CLOCK

DIGITAL DATA INPUTS (DB7–DB0)

Figure 12. Functional Block Diagram