AD9775EB datasheet(24/48 Pages) AD

24 / 48 page

REV. 0

AD9775

–24–

IQ PAIRING

(Control Register 02h, Bit 0)

In one port mode, the interleaved data is latched into the

AD9775 internal I and Q channels in pairs. The order of how

the pairs are latched internally is defined by this control register.

The following is an example of the effect this has on incoming

interleaved data.

Given the following interleaved data stream, where the data

indicates the value with respect to full scale:

0.5

With the control register set to “0” (I first), the data will appear

at the internal channel inputs in the following order in time:

I Channel

0.5

Q Channel

0.5

With the control register set to “1” (Q first), the data will appear at

the internal channel inputs in the following order in time:

I Channel

0.5

Q Channel

0.5

The values x and y represent the next I value and the previous

Q value in the series.

PLL DISABLED, TWO PORT MODE

With the PLL disabled, a clock at the DAC output rate must be

applied to CLKIN. Internal clock dividers in the AD9775 syn-

thesize the DATACLK signal at Pin 8, which runs at the input

data rate and can be used to synchronize the input data. Data is

latched into input Ports 1 and 2 of the AD9775 on the rising edge

of DATACLK. DATACLK speed is defined as the speed of

CLKIN divided by the interpolation rate. With zero stuffing

enabled, this division increases by a factor of 2. Figure 21

illustrates the delay between the rising edge of CLKIN and the

rising edge of DATACLK, as well as tS and tH in this mode.

The programmable modes DATACLK inversion and DATACLK

driver strength described in the previous section (PLL

Enabled, Two Port Mode) have identical functionality with

the PLL disabled.

As described earlier in the PLL-Enabled Mode section, tOD can

vary depending on CLKIN frequency and interpolation rate.

However, with the PLL disabled, the input data latches are

closely synchronized to DATACLK so that it is recommended

in this mode that the input data be timed from DATACLK, not CLKIN.

CLKIN

DATACLK

DATA AT PORTS

1 AND 2

tOD

tS = 5.0ns

tH = –3.2ns

(TYP SPECS)

Figure 21. Timing Requirements in Two Port

Input Mode with PLL Disabled

PLL DISABLED, ONE PORT MODE

In one port mode, data is received into the AD9775 as an inter-

leaved stream on Port 1. A clock signal (ONEPORT CLK),

running at the interleaved data rate which is 2

× the input data

rate of the internal I and Q channels is available for data syn-

chronization at Pin 32.

With PLL disabled, a clock at the DAC output rate must be applied

to CLKIN. Internal dividers synthesize the ONEPORTCLK

signal at Pin 32. The selection of the data for the I or Q channel

is determined by the state of the logic level applied to Pin 31

(IQSEL when the AD9775 is in one port mode) on the rising

edge of ONEPORTCLK. IQSEL = 1 under these conditions

will latch the data into the I channel on the clock rising edge,

while IQSEL = 0 will latch the data into the Q channel. It is

possible to invert the I and Q selection by setting control

illustrates the timing requirements for the data inputs as well as

the IQSEL input. Note that the 1

interpolation rate is not

available in the one port mode.

One port mode is very useful when interfacing with devices

such as Analog Devices’ AD6622 or AD6623 transmit signal

processors, in which two digital data channels have been inter-

leaved (multiplexed).

AD9775EB 数据表(PDF) 24 Page - Analog Devices

AD9775EB 数据表(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载