AD9831AST datasheet(2/16 Pages) AD

2 / 16 page

REV. A

–2–

AD9831–SPECIFICATIONS1

Parameter

AD9831A

Units

Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS

Resolution

Bits

Update Rate (fMAX)

MSPS nom

IOUT Full Scale

mA nom

mA max

Output Compliance

1.5

V max

DC Accuracy

Integral Nonlinearity

±1

LSB typ

Differential Nonlinearity

±0.5

LSB typ

DDS SPECIFICATIONS

Dynamic Specifications

Signal to Noise Ratio

dB min

fMCLK = 25 MHz, fOUT = 1 MHz

Total Harmonic Distortion

–53

dBc max

fMCLK = 25 MHz, fOUT = 1 MHz

Spurious Free Dynamic Range (SFDR)

fMCLK = 6.25 MHz, fOUT = 2.11 MHz

Narrow Band (

±50 kHz)

–72

dBc min

5 V Power Supply

–70

dBc min

3 V Power Supply

Wide Band (

±2 MHz)

–50

dBc min

Clock Feedthrough

–60

dBc typ

Wake-Up Time

ms typ

Powerdown Option

Yes

VOLTAGE REFERENCE

Internal Reference @ +25

°C

1.21

Volts typ

TMIN to TMAX

1.21

± 7%

Volts min/max

REFIN Input Impedance

Ω typ

Reference TC

100

ppm/

°C typ

REFOUT Output Impedance

300

Ω typ

LOGIC INPUTS

VINH, Input High Voltage

VDD – 0.9

V min

VINL, Input Low Voltage

0.9

V max

IINH, Input Current

µA max

CIN, Input Capacitance

pF max

POWER SUPPLIES

AVDD

2.97/5.5

V min/V max

DVDD

2.97/5.5

V min/V max

IAA

mA max

5 V Power Supply

IDD

2.5 + 0.33/MHz

mA typ

5 V Power Supply

IAA + IDD

mA max

3 V Power Supply

mA max

5 V Power Supply

Low Power Sleep Mode

mA max

1 M

Ω Resistor Tied Between REFOUT and AGND

NOTES

1Operating temperature range is as follows: A Version: –40

°C to +85°C.

2100% production tested.

MCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz.

4See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.

5Measured with the digital inputs static and equal to 0 V or DVDD.

6The Low Power Sleep Mode current is typically 2 mA when a 1 M

Ω resistor is not tied between REFOUT and AGND.

The AD9831 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenu-

ated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.

Specifications subject to change without notice.

(VDD = +3.3 V

10%; +5 V

10%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN =

REFOUT; RSET = 3.9 k ; RLOAD = 300

for IOUT unless otherwise noted)

IOUT

COMP

REFIN

ADJUST

REFOUT

AD9831

ON-BOARD

REFERENCE

10-BIT DAC

SIN

ROM

FULL-SCALE

CONTROL

300

Ω

50pF

RSET

3.9k

Ω

10nF

AVDD

Figure 1. Test Circuit with Which Specifications Are Tested

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