AD9831

–3–

REV. A

10%, +5 V

10%; AGND = DGND = 0 V, unless otherwise noted)

Limit at

Parameter

(A Version)

Units

Test Conditions/Comments

40

ns min

MCLK Period

16

ns min

MCLK High Duration

16

ns min

MCLK Low Duration

8

ns min

WR

Rising Edge to MCLK Rising Edge

8

ns min

WR

Rising Edge After MCLK Rising Edge

8

ns min

WR

Pulse Width

ns min

Duration between Consecutive WR Pulses

5

ns min

Data/Address Setup Time

3

ns min

Data/Address Hold Time

8

ns min

FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge

8

ns min

FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

ns min

RESET

Pulse Duration

*See Pin Description section.

Guaranteed by design but not production tested.

t

1

t

4

MCLK

WR

t

2

t

3

t

4A

t

6

t

5

Figure 2. Clock Synchronization Timing

A0, A1, A2

DATA

WR

t

8

t

5

t

7

t

6

VALID DATA

VALID DATA

Figure 3. Parallel Timing

VALID DATA

VALID DATA

VALID DATA

MCLK

FSELECT

PSEL0, PSEL1

RESET

t

9

t

10

t

9A

Figure 4. Control Timing