REV. B

ADC912A

–5–

WAFER TEST LIMITS

ADC912AG

Parameter

Symbol

Conditions

Limit

Unit

Integral Nonlinearity

INL

±1

LSB max

Differential Nonlinearity

DNL

±1

LSB max

Offset Error

Guaranteed by Design

±8

LSB max

Gain Error

±8

LSB max

Analog Input Resistance

4/6

k

Ω min/max

Logic Input High Voltage

CS, RD, HBEN

2.4

V min

Logic Input Low Voltage

CS, RD, HBEN

0.8

V max

Logic Input Current

CS, RD, HBEN

±1

µA max

Logic Output High Voltage

4

V min

Logic Output Low Voltage

0.4

V max

Positive Supply Current

7

mA max

Negative Supply Current

5

mA max

NOTE

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

NC

NC

NC

NC

NC

NC

NC

C1

C2

C1

C2

+

+

C1

C2

C1

C2

+

+

10V

–5V

+5V

–15V

R

R

R

R

R

R

R

R = 10

C1 = 0.01 F

C2 = 4.7 F

NC = NO CONNECT

POWER SUPPLY SEQUENCE:

+5V, –15V, –5V, +10V

ADC912A

TOP VIEW

(Not to Scale)

Figure 9. Burn-In Circuit