REV. B

ADC912A

–13–

SLOW-MEMORY MODE OPERATION USING WAIT

STATES

The WAIT state feature of the TMS32020 can also be used to

operate the ADC912A in the Slow-Memory mode. This is

accomplished by driving the clock input of the 7474 flip-flop in

Figure 23, from the BUSY output of the ADC912A, instead of

the CLK OUT 1 of the TMS32020. Once a conversion has

started the READY input of the TMS32020 is not released until

the ADC912A completes its 12-bit A/D conversion. This stops

the TMS32020 during the conversion process reducing micro-

processor system noise generation. Another advantage for the

system software is the single instruction IN MEM, PA used to

start, process, and read the results of the A/D conversion. This

makes the software code more transportable between systems

operating at different clock speeds. The disadvantage is some

loss in instruction processing time.

ADDRESS

DECODE

EN

ADDRESS BUS

DATA BUS

HBEN

ADC912A*

TMS32020

CS

RD

IS

*ESSENTIAL INTERFACE CIRCUITRY SHOWN FOR CLARITY

READY

R/W

BUSY

CK

7474

DQ

CLR

20MHz

2/CLK IN

"1"

SLOW-MEMORY

MODE

ROM MODE

(ONE WAIT STATE)

Figure 23. ADC912A to TMS32020 Interface Using Wait

States