REV. A

–7–

ADM706P/R/S/T, ADM708R/S/T

+1.2V

0V

+3V

1.3V

PFI

PFO

500ns/DIV

Figure 10. PFI Assertion Response Time

+1.3V

+3V

0V

1.2V

PFO

PFI

500ns/DIV

Figure 11. PFI Deassertion Response Time

0V

0V

100ns/DIV

RESET

+3V

RESET

+3V

Figure 12.

RESET, RESET Assertion

APPLICATIONS

A typical operating Circuit is shown in Figure 15. The unregu-

lated dc input supply is monitored using the PFI input via the

resistive divider network. Resistors R1 and R2 should be selected

such that when the supply voltage drops below the desired level

(e.g., 5 V) the voltage on PFI drops below the 1.25 V threshold

thereby generating an interrupt to the

µP. Monitoring the

preregulator input gives additional time to execute an orderly

shutdown procedure before power is lost.

ADM706

RESET

GND

P

MR

PFI

WDI

PFO

RESET

+3.3V

WDO

UNREGULATED

DC

I/O LINE

INTERRUPT

NMI

MANUAL

RESET

GND

GND

IN

OUT

ADM666A

Figure 15. Typical Application Circuit

+3V

0V

0V

+3V

100ns/DIV

RESET

RESET

Figure 13.

RESET, RESET Deassertion

+2V

0V

RESET

2 s/DIV

+3V

+3V

Figure 14. ADM706/ADM708

RESET Response Time