Parameter

ADMC201AP

Units

Conditions/Comments

ANALOG-TO-DIGITAL CONVERTER

1

Resolution

11

Bits

Twos Complement Data Format

Relative Accuracy

± 2

LSB max

Integral Nonlinearity

Differential Nonlinearity

± 2

LSB max

Bias Offset Error

± 5

LSB max

Any Channel

Bias Offset Match

4

LSB max

Between Channels

Full-Scale Error

± 6

LSB max

Any Channel

Full-Scale Error Match

4

LSB max

Between Channels

Conversion Time/Channel

40

System CLK Cycles

Signal-to-Noise Ratio (SNR)

2

60

dB min

Channel-to-Channel Isolation

Two-/Three-Phase Mode

–58

dB max

Sine Wave Applied to Unselected Channels

Three-/Three-Phase Mode

–55

dB max

ANALOG INPUTS

Input Voltage Level

0–5

Volts

Analog Input Current

100

µA max

Input Capacitance

10

pF typ

TRACK AND HOLD

Aperture Delay

200

ns max

Any Channel

Aperture Time Delay Match

20

ns max

Between Channels

SHA Acquisition Time

20

System CLK Cycles

Droop Rate

5

mV/ms max

REFERENCE INPUT

Voltage Level

2.5

V dc

Reference Input Current

50

µA max

REFERENCE OUTPUT

Voltage Level

2.5

Volts

Voltage Level Tolerance

± 5

% max

Full Load

Drive Capability

±200

µA max

LOGIC

0.8

V max

2.0

V min

0.4

V max

µA, V

4.5

V min

µA, V

Input Leakage Current

1

µA max

Three-State Leakage Current

1

µA max

Input Capacitance

20

pF typ

12-BIT PWM TIMERS

Resolution

12

Bits

Programmable Deadtime Range

0–10.08

µs

Programmable Deadtime Increments

2

System CLK Cycles

160 ns

Programmable Pulse Deletion Range

0–10.16

µs

Programmable Deletion Increments

1

System CLK Cycle

80 ns

Minimum PWM Frequency

1.5

kHz

Resolution Varies with PWM Switching Frequency

(10 MHz Clock: 20 kHz = 9 Bits, 10 kHz = 10 Bits,

5 kHz = 11 Bits, 2.5 kHz = 12 Bits). Higher Fre-

quencies are Available with Lower Resolution

VECTOR TRANSFORMATION

Park & Clarke Transformation

Radius Error

0.7

% max

Angular Error

30

arc min max

Reverse Transformation Time

37

System CLK Cycles

Forward Transformation Time

40

System CLK Cycles

EXTERNAL CLOCK INPUT

Range

6.25–25

MHz

If > 12.5 MHz, Then It Is Necessary to Divide Down

via SYSCTRL Register

INTERNAL SYSTEM CLOCK

Range

6.25–12.5

MHz

POWER SUPPLY CURRENT

20

mA max

NOTES

Specifications subject to change without notice.

ADMC201–SPECIFICATIONS

REV. B

–2–

5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = 12.5 MHz;