ADMC326 datasheet(13/31 Pages) AD

13 / 31 page

ADMC326

–13–

REV. A

The PWM is center-based. This means that in single update mode

the resulting output waveforms are symmetrical and centered in

the PWMSYNC period. Figure 7 presents a typical PWM tim-

ing diagram illustrating the PWM-related registers’ (PWMCHA,

PWMTM, PWMDT, and PWMSYNCWT) control over the

waveform timing in both half cycles of the PWM period. The

magnitude of each parameter in the timing diagram is determined

by multiplying the integer value in each register by tCK (typically

50 ns). It may be seen in the timing diagram how dead time is

incorporated into the waveforms by moving the switching edges

away from the instants set by the PWMCHA register.

PWMCHA

PWMDT

PWMSYNCWT + 1

PWMCHA

PWMTM

PWMSYNC

SYSSTAT (3)

PWMDT

Figure 7. Typical PWM Outputs of Three-Phase Timing

Unit in Single Update Mode

Each switching edge is moved by an equal amount (PWMDT

× t

CK) to preserve the symmetrical output patterns. The PWMSYNC

pulse, whose width is set by the PWMSYNCWT register, is also

shown. Bit 3 of the SYSSTAT register indicates which half cycle

is active. This can be useful in double update mode, as will be

discussed later.

The resultant on-times of the PWM signals shown in Figure 7

may be written as:

PWMCHA

PWMDT

PWMTM

PWMCHA

PWMDT

=×

(

–)

(–

–

)

The corresponding duty cycles are:

PWMCHA

PWMDT

PWMTM

PWMCHA

PWMDT

PWMTM

–

––

Obviously, negative values of TAH and TAL are not permitted

because the minimum permissible value is zero, corresponding

to a 0% duty cycle. In a similar fashion, the maximum value is

TS, corresponding to a 100% duty cycle.

The output signals from the timing unit for operation in double

update mode are shown in Figure 8. This illustrates a completely

general case where the switching frequency, dead time and duty

cycle are all changed in the second half of the PWM period. Of

course, the same value for any or all of these quantities could be

used in both halves of the PWM cycle. However, it can be seen

that there is no guarantee that symmetrical PWM signals will be

produced by the timing unit in this double update mode. Addi-

tionally, it is seen that the dead time is inserted into the PWM

signals in the same way as in the single update mode.

PWMCHA2

PWMSYNCWT2 + 1

PWMCHA1

PWMTM1

PWMTM2

PWMSYNCWT1 + 1

PWMSYNC

SYSSTAT (3)

PWMDT1

PWMDT2

Figure 8. Typical PWM Outputs of Three-Phase Timing

Unit in Double Update Mode

In general, the on-times of the PWM signals in double update

mode are defined by:

TAH = (PWMCHA1 + PWMCHA2 – PWMDT1

– PWMDT2 )

× t

TAL = (PWMTM1 + PWMTM2 – PWMCHA1

– PWMCHA2 – PWMDT1 – PWMDT2)

× t

where the subscript 1 refers to the value of that register during

the first half cycle and the subscript 2 refers to the value during

the second half cycle. The corresponding duty cycles are:

PWMCHA

PWMTM

PWMDT

PWMTM

PWMCHA

PWMTM

PWCHA

PWMDT

PWMTM

()

−

()

–

because for the completely general case in double update mode,

the switching period is given by:

TS = (PWMTM1 + PWMTM2)

× t

Again, the values of TAH and TAL are constrained to lie between

zero and TS.

PWM signals similar to those illustrated in Figure 7 and Figure

8 can be produced on the BH, BL, CH, and CL outputs by pro-

gramming the PWMCHB and PWMCHC registers in a manner

identical to that described for PWMCHA.

The PWM controller does not produce any PWM outputs until

all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC

registers have been written to at least once. After these registers

have been written, the counters in the three-phase timing unit

are enabled. Writing to these registers also starts the main PWM

timer. If during initialization, the PWMTM register is written

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