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ADMC326

–21–

REV. A

SYSTEM CONTROLLER

The system controller block of the ADMC326 performs the fol-

lowing functions:

Manages the interface and data transfer between the DSP

core and the motor control peripherals.

Handles interrupts generated by the motor control periph-

erals and generates a DSP core interrupt signal

IRQ2.

Controls the ADC multiplexer select lines.

Enables

PWMTRIP and PWMSYNC interrupts.

Controls the multiplexing of the SPORT1 pins to select

either DR1A or DR1B data receive pins. It also allows con-

figuration of SPORT1 as a UART interface.

Controls the PWM single/double update mode.

Controls the ADC conversion time modes.

Controls the auxiliary PWM operation mode.

Contains a status register (SYSSTAT) that indicates the

state of the

PWMTRIP pin, the watchdog timer and the

PWM timer.

10. Performs a reset of the motor control peripherals and con-

trol registers following a hardware, software or watchdog

initiated reset.

SPORT1 Control

Both data receive pins are multiplexed internally into the single

data receive input of SPORT1 as shown in Figure 18. Two

control bits in the MODECTRL register control the state of

the SPORT1 pins by manipulating internal multiplexers in

the ADMC326.

DSP

CORE

SPORT1

PIO4/DR1A

PIO2/DR1B

PIO0/TFS1

PIO5/RFS1

PIO3/SCLK1

MODECTRL (5 . . . 4)

UARTEN

DR1SEL

DT1

DR1

TFS1

RFS1

SCLK1

FL1

ADMC326

PIO1/DT1

Figure 18. Internal Multiplexing of SPORT1 Pins

Bit 4 of the MODECTRL register (DR1SEL) selects between

the two data receive pins. Setting Bit 4 of MODECTRL con-

nects pin DR1B to the internal data receive port DR1 of SPORT1.

Clearing Bit 4 connects DR1A to DR1.

Setting Bit 5 of the MODECTRL register (SPORT1 Mode)

configures the serial port for UART mode. In this mode, the

DR1 and RFS1 pins of the internal serial port are connected to-

gether. Additionally, setting the SPORT1 Mode bit connects

the FL1 flag of the DSP to the external PIO5/RFS1 pin.

Flag Pins

The ADMC326 provides flag pins. The alternate configuration

of SPORT1 includes a Flag In (FI) and Flag Out (FO) pin.

This alternate configuration of SPORT1 is selected by Bit 10 of

the DSP system control register, SYSCNTL at data memory

address, 0x3FFF. In the alternate configuration, the DR1 pin

(either DR1A or DR1B depending upon the state of the DR1SEL

bit) becomes the FI pin and the DT1 pin becomes the FO pin.

Additionally, RFS1 is configured as the

IRQ0 interrupt input

and TFS1 is configured as the

IRQ1 interrupt. The serial port

clock, SCLK1, is still available in the alternate configuration.

Development Tools

Users are recommended to obtain the ADMCF326-EVALKIT

from Analog Devices. The tool kit contains everything required

to quickly and easily evaluate and develop applications using the

ADMCF326 and ADMC326 DSP Motor Controllers. Please

contact your ADI sales representative for ordering information.

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