ADP3413 datasheet(2/8 Pages) AD

2 / 8 page

REV. 0

–2–

ADP3413–SPECIFICATIONS1

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SUPPLY

Supply Voltage Range

VCC

4.15

7.5

Quiescent Current

ICCQ

OD INPUT

Input Voltage High

2.0

Input Voltage Low2

0.8

Propagation Delay Time

tpdlOD

tpdhOD

PWM INPUT

Input Voltage High

2.3

Input Voltage Low

0.8

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current

VBST – VSW = 5 V

3.0

5.0

Ω

VBST – VSW = 7 V

2.0

3.5

Ω

Output Resistance, Sinking Current

VBST – VSW = 5 V

1.25

2.5

Ω

VBST – VSW = 7 V

1.0

2.5

Ω

Transition Times

3 (See Figure 2)

trDRVH

VBST – VSW = 7 V, CLOAD = 3 nF

tfDRVH

VBST – VSW = 7 V, CLOAD = 3 nF

Propagation Delay

3, 4 (See Figure 2)

tpdhDRVH

VBST – VSW = 7 V

tpdlDRVH

VBST – VSW = 7 V

LOW-SIDE DRIVER

Output Resistance, Sourcing Current

VCC = 5 V

3.0

5.0

Ω

VCC = 7 V

2.0

3.5

Ω

Output Resistance, Sinking Current

VCC = 5 V

1.5

3.0

Ω

VCC = 7 V

1.0

2.5

Ω

Transition Times3 (See Figure 2)

trDRVL

VCC = 7 V, CLOAD = 3 nF

tfDRVL

VCC = 7 V, CLOAD = 3 nF

Propagation Delay

3, 4 (See Figure 2)

tpdhDRVL

VCC = 7 V

tpdlDRVL

VCC = 7 V

NOTES

1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2Logic inputs meet typical CMOS I/O conditions for source/sink current (~1

µA).

3AC specifications are guaranteed by characterization, but not production tested.

4For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.

Specifications subject to change without notice.

(TA = 0 C to 70 C, VCC = 7 V, BST = 4 V to 26 V, OD > 2 V, unless otherwise noted.)

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