REV. 0

–3–

ADP3413

PINCONFIGURATION

IN

VCC

BST

DRVH

SW

DRVL

PGND

8

7

6

5

1

2

3

4

ADP3413

OD

TOP VIEW

(Not To Scale)

ABSOLUTE MAXIMUM RATINGS

*

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V

BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V

BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V

SW

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V

OD, IN . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V

Operating Ambient Temperature Range . . . . . . . 0

°C to 70°C

Operating Junction Temperature Range . . . . . . 0

°C to 125°C

θ

JC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

°C/W

Storage Temperature Range . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300

°C

*This is a stress rating only; operation beyond these limits can cause the device to

be permanently damaged. Unless otherwise specified, all voltages are referenced

to PGND.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADP3413 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN FUNCTION DESCRIPTIONS

Pin

Mnemonic

Function

1

BST

Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW pins

holds this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be

chosen between 100 nF and 1 F.

2

IN

TTL-level Input Signal, which has primary control of the drive outputs.

3

OD

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

4

VCC

Input Supply. This pin should be bypassed to PGND with ~1

µF ceramic capacitor.

5

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

6

PGND

Power Ground. Should be closely connected to the source of the lower MOSFET.

7

SW

This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating

return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-

on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the

high-low transition delay is determined at this pin.

8

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

ORDERING GUIDE

Temperature Package

Package

Model

Range

Description

Option

ADP3413JR 0

°C to 70°C

8-Lead Standard

SO-8

Small Outline (SOIC)