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ADSP2181 数据表(PDF) 23 Page - Analog Devices |
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ADSP2181 数据表(HTML) 23 Page - Analog Devices |
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23 / 32 page  ADSP-2181 –23– REV. D Parameter Min Max Unit IDMA Read, Long Read Cycle Timing Requirements: tIKR IACK Low before Start of Read1 0ns tIRP Duration of Read 15 ns Switching Characteristics: tIKHR IACK High after Start of Read1 15 ns tIKDS IAD15–0 Data Setup before IACK Low 0.5tCK – 10 ns tIKDH IAD15–0 Data Hold after End of Read 2 0ns tIKDD IAD15–0 Data Disabled after End of Read 2 12 ns tIRDE IAD15–0 Previous Data Enabled after Start of Read 0 ns tIRDV IAD15–0 Previous Data Valid after Start of Read 15 ns tIRDH1 IAD15–0 Previous Data Hold after Start of Read (DM/PM1) 3 2tCK – 5 ns tIRDH2 IAD15–0 Previous Data Hold after Start of Read (PM2) 4 tCK – 5 ns NOTES 1Start of Read = IS Low and IRD Low. 2End of Read = IS High or IRD High. 3DM read or first half of PM read. 4Second half of PM read. tIRP tIKR PREVIOUS DATA READ DATA tIKHR tIKDS tIRDV tIRDH tIKDD tIRDE tIKDH IAD15–0 IACK IS IRD Figure 17. IDMA Read, Long Read Cycle |
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