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SMP04ES 数据表(PDF) 4 Page - Analog Devices

部件名 SMP04ES
功能描述  CMOS Quad Sample-and-Hold Amplifier
PDF  15 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SMP04ES 数据表(HTML) 4 Page - Analog Devices

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–4–
SMP04
REV. D
WAFER TEST LIMITS
SMP04G
Parameter
Symbol
Conditions
Limits
Units
Buffer Offset Voltage
VOS
VIN = +6 V
±10
mV max
Hold Step
VHS
VIN = +6 V
±4
mV max
Droop Rate
∆V/∆tV
IN = +6 V
25
mV/s max
Output Source Current
ISOURCE
VIN = +6 V
1.2
mA min
Output Sink Current
ISINK
VIN = +6 V
0.5
mA min
Output Voltage Range
OVR
RL = 20 kΩ
0.06/10.0
V min/max
RL = 10 k
0.06/9.5
V min/max
LOGIC CHARACTERISTICS
Logic Input High Voltage
VINH
2.4
V min
Logic Input Low Voltage
VINL
0.8
V max
Logic Input Current
IIN
1
µA max
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
PSRR
10.8 V
≤ V
DD
≤ 13.2 V
60
dB min
Supply Current
IDD
7
mA max
Power Dissipation
PDIS
84
mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
(@ VDD = +12 V, VSS = DGND = 0 V, RL = No Load, TA = +25 C, unless otherwise noted.)
VOUT3
VOUT1
VOUT2
VOUT4
VIN1
VIN2
VIN3
VIN4
S/H1
S/H3
S/H4
DGND
VSS
VDD
S/H2
Dice Characteristics
Die Size: 0.80 x 0.120 mil = 9,600 sq. mil
(2.032 x 3.048mm = 6.193 sq. mm)



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