A d v a nce d I n fo rm a t i o n

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Linear Technology / Dust Networks

Eterna Datasheet

2.1.1

Supply Monitoring and Reset

Eterna integrates an Power on Reset (PoR) circuit and as the RESETn input pin is nominally configured with an internal pull-

up resistor, thus no connection is required. For a graceful shutdown, the software and networking layers be cleanly halted

prior to assertion of the RESETn pin. Eterna includes a soft brown-out monitor that fully protects the Flash from corruption

in the event that power is removed while writing to flash. Integrated flash supervisory functionality in conjunction with ***

(do we do a JFS?) yields a robust non-volatile file system.

2.2

Precision Timing

Eterna, differs from competing 802.15.4 product offerings by providing low-power dedicated timing hardware and timing

algorithms that provide timing precision two to three orders of magnitude better than any other available low-power solution.

Improved timing accuracy allows motes to minimize the amount of radio listening time required to ensure packet reception

thereby lowering even further the power consumed by an Eterna network. Eterna’s patented timing hardware and timing

algorithms provide superior performance over rapid temperature changes, further differentiating Eterna’s reliability when

compared with other wireless products. In addition, precise timing enables networks to reduce spectral dead time, increasing

total network throughput.

2.2.1

Time Synchronization

In addition to coordinating timeslots across the network, which is transparent to the user, Eterna’s unparalleled timing

management is used to support two mechanisms to share network time. Having an accurate, shared, network-wide time base

enables events to be accurately time stamped or tasks to be performed in a synchronized fashion across a network. Eterna

will send a time packet through its serial interface when one of the following occurs:

•

Eterna receives an HDLC request to read time

•

The TIMEn signal is asserted

The use of TIMEn has the advantage of being more accurate. The value of the timestamp is captured in hardware relative to

the rising edge of TIMEn. If the HDLC request is used, due to packet processing the value of the timestamp may be captured

several milliseconds after receipt of the packet. See Section 8.10 for the time functions definition and specifications.

2.3

Time References

Eterna includes three clock sources: a low power oscillator designed for a 32.768 kHz crystal, the radio reference oscillator

designed for a 20 MHz crystal, and an internal relaxation oscillator.

2.3.1

Relaxation Oscillator

The relaxation oscillator is the primary clock source for Eterna, providing the clock for the CPU, memory subsystems, and all

peripherals. The internal relaxation oscillator typically starts up in a few

μs, providing an expedient, low-energy method for

duty cycling between active and low power states. Quick start-up from the doze state, defined in section 4.0, allows Eterna to

wake up and receive data over the UART and SPI interfaces by simply by detecting activity the appropriate signals.

2.3.2

32.768 kHz Crystal

Once Eterna is powered up and the 32.768 kHz crystal source has begun oscillating, the 32.768 kHz crystal remains

operational while in the Active state, and is used as the timing basis when in Doze state. See Section 4.0 for a description of

Eterna’s operational states.

2.3.3

20 MHz Crystal

The 20 MHz crystal source provides a frequency reference for the radio, and is automatically enabled and disabled by Eterna

as needed.

2.4

Radio

Eterna is the lowest-power commercially available 2.4 GHz IEEE 802.15.4e radio by a substantial margin. (Please refer to

section 8.2 for power consumption numbers.). Eterna’s integrated power amplifier is calibrated and temperature-compensated

to consistently provide power at a limit suitable for worldwide radio certifications. Additionally, Eterna uniquely includes a