A d v a nce d I n fo rm a t i o n

Eterna Datasheet

Linear Technology / Dust Networks

9

2.8.2

Sleep

The SLEEPn digital interrupt enables an external controller to temporarily disable Eterna’s duty cycling between active and

Doze states (see Section 4.0 for state definitions). Forcing Eterna to the Doze state should only be done when absolutely

necessary, such as when taking a very sensitive sensor reading, as forcing a device into a Doze state will on the average

increase the energy consumption of other devices in the network. When SLEEPn is asserted the software will go into a Doze

state until the SLEEPn signal is negated. For details on the timing associated with SLEEPn, see Section 8.11.

2.10

Flash Programming

Eterna’s software images are loaded via the IPCS, in-circuit programming control system, SPI interface. Sequencing of

RESETn and FLASH_P_ENn, as described in Section 4.0, places Eterna in a state emulating a serial flash to support in-

circuit programming. Hardware and software for supporting development and production programming of devices is

described in 040-0110 Eterna Serial Programmer Guide. The serial protocol, SPI, and timing parameters are described in

Section 8.13.

4.0

Operation

In order to provide capabilities and flexibility in addition to ultra low power, Eterna operates in various states, as shown in

Figure 8 and described in this section.

CPU and peripherals

inactive

RESETn low and

FLASH_P_ENn low

lowPowerSleep

Command

Operation

Set RESETn high and

FLASH_P_EN high

for 125 µs, then

set RESETn low

Load Fuse

Settings

Serial Flash

Emulation

Reset

Doze

Deep Sleep

Active

Power-On

Reset

Start Up

Inactive

HW or PMU Event

RESETn low and

FLASH_P_ENn high

VSUPPLY > PoR

De-assert RESETn

Boot

Assert RESETn

Assert RESETn

Assert RESETn

Figure 8

State Diagram – Operating Modes

4.1

Start Up

Start Up occurs as a result of either tripping of the power-on-reset circuit or the assertion of RESETn. After the completion

of power-on-reset (see Section 2.1.1) or the falling edge of an internally synchronized RESETn, Eterna loads its Fuse Table

(see section 4.1.1), including setting I/O direction. In this state, Eterna checks the state of the FLASH_P_ENn and RESETn