ACT3492 datasheet(11/49 Pages) AEROFLEX

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Aeroflex Circuit Technology

SCD3492 REV B 6/26/01 Plainview NY (516) 694-6700

fault coverage. The monolithic circuit includes all circuitry required to perform the self-test.

Self-test can be an on-line or off-line function which is initiated by simple subsystem intervention. The

DRVINH signal selects on-line or off-line testing.

The circuit accomplishes the on-line test without

accessing the MIL-STD-1553 data bus by providing an internal data path which connects the encoder

circuitry directly to the decoder circuitry. The transceiver is inhibited during this on-line test. The off-line

test is designed to include the transceiver as well as the protocol device. This mode will generally be useful

as an off-line card test where no live bus is in use.

To initiate the self-test a word is placed in the Vector Word Latch, Loop Test Enable (LTEN) is held low, and

the Loop Test Trigger (LTTRIG) signal is pulsed low. The primary bus will be tested with the word that

resides in the Vector Word Latch, encoded then looped back, decoded and presented to the subsystem as

a normal data transfer would be accomplished. The secondary bus is sequentially tested after the primary

bus is completed via Request Bus A (REQBUSA) utilizing the same word residing in the Vector Word

Latch. Upon completion of each test, pass/fail signals will be asserted reporting the results of the test.

This test implementation verifies MIL-STD-1553 protocol compliance; proper sync character, 16 data bits,

Manchester II coding, odd parity, contiguous word checking and a bit by bit comparison of the transmitted

data.

The self-test circuitry increases the fault coverage by insuring that the internal function blocks;

encoder, decoder, and internal control circuitry are operating correctly.

An effective data pattern to

accomplish this is HEX AA55 since each bit is toggled, (8 bit internal highway) on a high/low byte basis.

The total time required to complete the self-test cycle is 89 microseconds. The Loop Test Enable signal

must remain in the low state throughout the diagnostic cycle.

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