OR3LP26B datasheet(21/184 Pages) AGERE

21 / 184 page

Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port

Pages 21—69 will refer to the dual-port mode of the OR3LP26B device. For quad-port mode, please refer to pages

70—122.

Embedded Core/FPGA Interface Signal Descriptions

In Table 8, an input refers to a signal flowing into the FPGA logic (out of the embedded core) and an output refers

to a signal flowing out of the FPGA logic (into the embedded core).

Table 8. Embedded Core/FPGA Interface Signals

Symbol

I/O

Description

Data FIFO Signals

datafmfpga[63:0]

datafmfpgax[7:0]

Main data bus into the master write FIFO and target read FIFO. Refer to Table 10 on

page 30 for bus usage and bit descriptions.

These signals must be synchronous to fclk.

datatofpga[63:0]

datatofpgax[7:0]

Main data bus out of the master read FIFO and target write FIFO. Refer to Table 10

on page 30 for bus usage and bit descriptions.

These signals are synchronous to fclk.

Master General Signals

fpga_mbusyn

FPGA Master Is Busy. This signal is used in modes currently not implemented in the

core. Tie off this signal to a 1.

fpga_msyserror

FPGA Master Cycle Aborted by PCI Target. The PCI Master controller in the PCI

core asserts this active-high as an indication that the current cycle to the PCI bus has

been aborted. This signal is synchronous to fclk.

mcfgshiftenn

pci_mcfg_stat

mcfgshiftenn is an active-low signal that determines the data that is output by the PCI

core onto signal pci_mcfg_stat:

mcfgshiftenn = 1: pci_mcfg_stat = wired-OR of all bits below, after being

masked by FPGA configuration RAM bits;

mcfgshiftenn = 0: pci_mcfg_stat = each bit below, one at a time on succes-

sive pciclk rising edges (unmasked), reset when

mcfgshiftenn = 1;

Status bits:

Data parity error detected, Target abort received, and

Master abort received.

Both signals are synchronous to fclk.

Master FIFO Address and Command Register Control Signals

Symbol

I/O

Description

maenn

Master Command/Address/Burst Length Enable. This is an active-low signal and

is used to enable registering commands, burst length, and start address into the Mas-

ter address register of the PCI core. On each rising edge of the clock that this signal

is sampled low, command, burst length, and address will be registered.

This signal must be synchronous to fclk.

ma_fulln

Master Address Register Full Flag. This active-low signal indicates that the Master

address register is full and no more addresses can be registered.

This signal is synchronous to fclk.

mstatecntr[2:0]

Internal State Counter. Used for Master reads and writes. Details of the Master state

machine operation can be found in tables at the end of each operation section.

This signal is synchronous to fclk.

mfifoclrn

Master FIFO Clear. This active-low signal is asserted by the FPGA Master to clear all

Master FIFOs.

This signal must be synchronous to fclk.

OR3LP26B 数据表(PDF) 21 Page - Agere Systems

OR3LP26B 数据表(HTML) 21 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载