OR3LP26B datasheet(49/184 Pages) AGERE

49 / 184 page

Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual

Port (continued)

Target (PCI Bus Initiated) Write

Operation Setup

The FPGA application waits for Target request, treqn,

from the PCI core to become active, indicating a Target

operation, either read or write. It then asserts Target

address enable, taenn, to clock out the command and

its address. Table 21 describes the specific order of

operation for a Target write transaction.

Bursts can be of any length, but will disconnect when

any of the following conditions occur:

tw_fulln is asserted low, and twburstpendn is deas-

serted high.

The maximum number of wait-states has been

inserted.

The BAR boundary has been crossed.

Target State Counter

The PCI core provides a state counter, tstatecntr[2:0],

that informs the FPGA of the current state of the PCI

core's Target state counter. This state counter deter-

mines what data is currently being provided by the PCI

core or expected from the FPGA application. This state

counter transitions from one state to another in a pre-

dictable fashion, and thus, it is not strictly necessary to

transmit its value to the FPGA. Nonetheless, the value

on bus tstatecntr can be used to minimize FPGA logic

or verify proper operation.

The data provided by the PCI core to the FPGA appli-

cation on bus datatofpga is accompanied by a value

on bus tstatecntr. This value can be directly used by

the FPGA application to determine the proper use of

that data. This eliminates the need for logic in the

FPGA to duplicate these state counters in this case.

The data required from the FPGA application by the

PCI core on bus datafmfpga is also defined by the

value on bus tstatecntr. However, the state counter

value is being sent to the FPGA in the same cycle that

the data must be sent from the FPGA. Therefore, the

FPGA application must build its own copy of the state

counter value in this case. The value provided by the

PCI core can be used as the previous value, or it can

be used to verify the proper operation of the FPGA

application's logic.

Table 10 lists the values of the state counter tstatecntr

and the appropriate accompanying data.

Data Transfer

For a Target write data transfer, the FPGA application

begins receiving the supplied data by deasserting

taenn and asserting twdataenn. On every cycle that

twdataenn is asserted, the FPGA application clocks

data out of the PCI core’s Target write FIFO (32 deep

by 36 bits wide in 32-bit PCI mode; 16 deep by 72 bits

wide in 64-bit PCI mode) via bus datatofpga.

FIFO Empty/Almost Empty

Data to be written is buffered in the Target write FIFO

(32 deep by 36 bits wide in 32-bit PCI mode; 16 deep

by 72 bits wide in 64-bit PCI mode). When this FIFO

contains four or fewer data elements, the PCI core

asserts tw_aempty, the FIFO almost empty indicator.

This allows some latency to exist in the FPGA’s

response without risking overreading the FIFO. When

the PCI core has read all data out of the Target write

FIFO, the PCI core asserts tw_emptyn, the FIFO

empty indicator. Since data can be simultaneously writ-

ten to and read from the Target write FIFO, both

tw_aemptyn and tw_emptyn can change states in

either direction multiple times in the course of a burst

data transfer.

FIFO Full

In addition to the empty and almost empty signals that

report when the Target write FIFO is currently unable to

supply data to the FPGA application, the PCI core also

provides the FIFO's full signal. If the FIFO does go full,

the core will do one of two things. If twburstpendn is

deasserted high, the target will disconnect. If twburst-

pendn is asserted low, the target will assert up to eight

wait-states and then disconnect if still full. The FIFO full

flag is not generally used in user designs. If it is, how-

ever, keep in mind that it is synchronous to pciclk.

Bursting

Signal twlastcycn tells the FPGA application whether

the current write is a burst. The FPGA application con-

tinues to unload data from the FIFO as long as twlast-

cycn is inactive. The bursting will continue until either

twlastcycn is received, the FIFO becomes full, or the

BAR boundary is crossed. There is no fixed maximum

transfer word count.

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