ADAU7002ACBZ-R7 datasheet(3/16 Pages) AD

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Data Sheet

ADAU7002

Rev. 0 | Page 3 of 16

SPECIFICATIONS

IOVDD = 1.8 V, TA = 25°C, BCLK = 3.072 MHz, output = 48 kHz, I2S format, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL INPUT/OUTPUT

High Level Input Voltage (VIH)

0.7 × IOVDD

Low Level Input Voltage (VIL)

0.3 × IOVDD

Input Leakage, High (IIH)

BCLK and LRCLK pins

µA

Input Leakage, Low (IIL)

BCLK and LRCLK pins

µA

Input Capacitance

SDATA

4.5

PDM_CLK

PERFORMANCE

Dynamic Range

20 Hz to 20 kHz, −60 dB input

With A-Weighted Filter (RMS)

110

Signal-to-Noise-Ratio

A-weighted, fourth-order input

110

Decimation Ratio

64×

Frequency Response

DC to 0.45 output fS

−0.1

+0.01

Stop Band

0.566

Stop-Band Attenuation

Group Delay

0.02 fS input signal

3.31

LRCLK cycles

Gain

PDM to PCM

Start-Up Time

LRCLK cycles

Bit Width

Internal and output

Bits

Interchannel Phase

Degrees

CLOCKING

Output Sampling Rate

fS LRCLK pulse rate

kHz

BCLK Frequency

fBCLK

0.256

3.072

24.576

MHz

POWER SUPPLIES

Supply Voltage Range

IOVDD

1.62

3.6

Supply Current

IOVDDSY = 1.8 V

0.67

IOVDD = 3.3 V

1.33

IOVDD = 1.8 V, 16 kHz output

0.21

IOVDD = 3.3 V, 16 kHz output

0.41

Shutdown Current

IOVDDSD, no input clocks

µA

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