Data Sheet

ADAU7002

Rev. 0 | Page 9 of 16

APPLICATIONS INFORMATION

OVERVIEW

The ADAU7002 provides stereo decimation from a 1-bit PDM

source to a 20-bit PCM audio. The downsampling ratio is fixed

at 64×. The 20-bit downsampled PCM audio is output via

The input source for the ADAU7002 can be any device that has

a PDM output, such as a digital microphone like the ADMP521.

The output pins of these microphones can connect directly to

the input pins of the ADAU7002.

CLOCKING

The ADAU7002 requires a BCLK rate that is a minimum of 64×

the LRCLK sample rate. BCLK rates of 128×, 192×, 256×, 384×,

and 512× the LRCLK rate are also supported. The ADAU7002

automatically detects the ratio between BCLK and LRCLK and

generates a PDM clock output at 64× the LRCLK rate. The

minimum sample rate is 4 kHz, and the maximum is 96 kHz,

which correspond to a PDM clock range of 256 kHz to 6.144 MHz.

Internally, all processing is done at the PDM_CLK rate.

When BCLK is removed, the ADAU7002 powers down

automatically. When BCLK is not present, the PDM_CLK

output stops.

Table 5. PDM Timing Parameters

Parameter

Unit

10

ns

7

ns

PDM data is latched on both edges of the clock.

Figure 11. PDM Timing Diagram

SERIAL AUDIO OUTPUT INTERFACE

Format selection and TDM slot placement is set with the CONFIG

pin. The SDATA pin is in tristate mode, except when the port is

driving serial data based on the CONFIG pin configuration.

Table 6. TDM Slot Selection

Device Setting

CONFIG Pin Configuration

Tie to IOVDD

TDM Slot 1 to Slot 2 Used/Driven, 32-Bit Slots

Tie to GND

TDM Slot 3 to Slot 4 Used/Driven, 32-Bit Slots

Open

TDM Slot 5 to Slot 6 Used/Driven, 32-Bit Slots

Tie to IOVDD through a 47 kΩ resistor

TDM Slot 7 to Slot 8 Used/Driven, 32-Bit Slots

Tie to GND through a 47 kΩ resistor

R

L

PDM_CLK

PDM_DAT

R

L