ADL5303

Data Sheet

Rev. 0 | Page 12 of 24

USING THE ADL5303

The default configuration (see Figure 25) includes a 2.5:1 atten-

uator in the feedback path around the buffer. This increases the

slope of 10 mV/dB at the VLOG pin to 25 mV/dB at VOUT.

For the full dynamic range of 160 dB (80 dB optical), the output

swing is 4.0 V, which can be accommodated by the rail-to-rail

output stage when using the recommended 5 V supply.

The capacitor from VLOG to ground forms an optional

single-pole low-pass filter. Because the resistance at this pin

is trimmed to 5 kΩ, an accurate time constant can be realized.

3.2 kHz. Such filtering is useful in minimizing the output noise,

effective in reducing noise. A capacitor between VSUM and

ground is essential for minimizing the noise on this node.

When the bias voltage at either VPDB or VREF is not needed,

these pins should be left unconnected.

SLOPE AND INTERCEPT ADJUSTMENTS

The choice of slope and intercept depends on the application.

The versatility of the ADL5303 permits optimal choices to

be made in two common situations. First, it allows an input

current range of less than the full 160 dB to use the available

voltage span at the output. Second, it allows this output voltage

range to be optimally positioned to fit the input capacity of a

subsequent ADC. In special applications, very high slopes, such

sensitivity.

The slope can be lowered without limit by the addition of a

at this pin is trimmed to 5 kΩ, the accuracy of the modified

slope depends on the external resistor. It is calculated by,

kΩ

5

+

=

S

S

Y

Y

R

R

V

V

(8)

decade or 3.75 mV/dB. Table 4 provides a selection of suitable

Table 4. Examples of Lowering the Slope

3

75

5

100

15

150

In addition to uses in filter and comparator functions, the

buffer amplifier provides the means to adjust both the slope

and intercept, which require a minimal number of external

components. The high input impedance at BFIN, low input

offset voltage, large output swing, and wide bandwidth of this

signal, using standard op amp circuit practices. For example, it

has been noted that to raise the gain of the buffer, and therefore

be inserted between VLOG and the inverting input BFNG pin.

NC

500mV/DEC

200mV/DEC

10k

Ω

~10k

Ω

15kΩ

5k

Ω

NC

NC = NO CONNECT

100nF

R1

750

C1

1nF

C3

PDB

BIAS

VREF

VPDB

VSUM

INPT

VSUM

ACOM

VPS2

PWDN

VPS1

VREF

VLOG

BFIN

BFNG

VOUT

0.5V

ADL5303

5

2

3

4

15

14

GND

GND

7

11

10

16

12

6

8

9

13

TEMPERATURE

COMPENSATION

Figure 25. Basic Connections (R15, R18, C7 are Optional; R1 and C1 are the Default Values)