Data Sheet

ADL5906

Rev. 0 | Page 29 of 32

Component

Function/Notes

Default Value

VOUT, VOUT1,

VSET, R1, R2,

R6, R15

Output interface. In measurement mode, a portion of the voltage at the VRMS pin is fed back

to the VSET pin via R6 (R6 is normally set to 0 Ω). Using the voltage divider created by R2 and

back to VSET. Resistors R1 and R15 can be used to reduce the output slope.

VOUT = black test loop,

VOUT1 = SMA connector,

VSET = black test loop,

R1 = R6 = 0 Ω,

R15 = R2 = open

In controller mode, R6 must be open. In this mode, the ADL5906 can control the gain of a variable

gain amplifier (VGA) or voltage variable attenuator (VVA). A setpoint voltage is applied to the

VSET test loop, and the VRMS test loop or SMA connector drives the gain control input of the

VGA/VVA.

C9

RMS averaging capacitor. The value of the rms averaging capacitor should be set based on the

peak-to-average ratio of the input signal and based on the desired output response time and

residual output noise.

C9 = 0.1 µF

TC2, R9, R12

TADJ/PWDN interface. The TADJ/PWDN pin controls the slope temperature compensation

and/or shuts down the device. The evaluation board is configured with VTADJ connected to

VREF through a resistor divider (R9, R12). This voltage divider can be removed (or simply

overdriven) allowing for the external application of a voltage to the VTADJ pin by applying a

voltage to the TC2 test point.

TC2 = black test loop,

R9 = 1.5 kΩ, R12 = 270 Ω,

VTADJ = 0.35 V

EVALUATION BOARD ASSEMBLY DRAWINGS

Figure 64. ADL5906 Evaluation Board Layout, Top Side

Figure 65. ADL5906 Evaluation Board Layout, Bottom Side