ADL5906ACPZN-R7 datasheet(17/32 Pages) AD

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Data Sheet

ADL5906

Rev. 0 | Page 17 of 32

When forcing the previous identity by varying the VGA setpoint, it

is apparent that

RMS(VSIG) = √(Mean(VSIG2)) = √(VATG2) = VATG

(5)

Substituting the value of VSIG from Equation 2 results in

RMS(G0 × RFIN e

)

(

GNS

SET

−

) = VATG

(6)

When connected as a measurement device, VSET = VRMS. Solving

for VRMS as a function of RFIN,

VRMS = VSLOPE × log10(RMS(RFIN)/VZ)

(7)

where:

VSLOPE = 1.12 V/decade (or 56 mV/dB) at 2.14 GHz.

VZ is the intercept voltage.

When RMS(RFIN) = VZ, this implies that VRMS = 0 V because

log10(1) = 0. This makes the intercept the input that forces VRMS =

0 V if the ADL5906 had no sensitivity limit.

In most applications, the AGC loop is closed through the setpoint

interface and the VSET pin. In measurement mode, VRMS is

directly connected to VSET (see the Measurement Mode Basic

Connections section for more information). In controller mode,

a control voltage is applied to VSET, and the VRMS pin typically

drives the control input of an amplification or attenuation system.

In this case, the voltage at the VSET pin forces a signal amplitude

at the RF inputs of the ADL5906 that balances the system through

feedback.

RF INPUT INTERFACE

Figure 42 shows the RF input connections within the ADL5906.

Two internal 2.5 kΩ resistors connected between RFIN+ and RFIN−

primarily set the input impedance. A dc level of approximately

half the supply voltage on each pin is established internally at

the center point of the bias resistors. Either the RFIN+ or the

RFIN− pin can be used as the single-ended RF input pin. Connect

signal coupling capacitors from the input signal to the RFIN+

and RFIN− pins. A single external 60.4 Ω resistor to ground

from the desired input creates an equivalent 50 Ω impedance

over a broad section of the operating frequency range. RF ac-couple

the other input pin to common (ground). The input signal high-

pass corner formed by the internal and external resistances of

the input coupling capacitor is

fHIGHPASS = 1/(2 × π × 50 × C)

(8)

where C is the capacitance in farads, and fHIGHPASS is in hertz.

The input coupling capacitors must be large enough in value to

pass the input signal frequency of interest and determine the low

end of the frequency response. RFIN+ and RFIN− can also be

driven differentially using a balun.

ESD

RFIN–

RFIN+

VPOS

VBIAS

GND

LOAD

2.5kΩ

Figure 42. RF Inputs

Extensive ESD protection is employed on the RF inputs, and this

protection limits the maximum possible input to the ADL5906.

TEMPERATURE SENSOR INTERFACE

The ADL5906 provides a temperature sensor output with a scaling

factor of the output voltage of approximately 4.8 mV/°C. The

output is capable of sourcing 4 mA and sinking 50 µA maximum

at 25°C. An external resistor can be connected from VTEMP to

GND to provide additional current sink capability. The typical

output voltage at 25°C is approximately 1.4 V.

VTEMP

VPOS

GND

INTERNAL

VPAT

12kΩ

4kΩ

Figure 43. TEMP Interface Simplified Schematic

VREF INTERFACE

The VREF pin provides an internally generated voltage reference

for the user. The VREF voltage is a temperature stable 2.3 V

reference that is capable of sourcing 4 mA and sinking 50 µA

maximum. An external resistor can be connected from VREF

to GND to provide additional current sink capability. The

voltage on this pin can be used to drive the TADJ/PWDN and

VTGT pins.

INTERNAL

VOLTAGE

16kΩ

VREF

VPOS

GND

Figure 44. VREF Interface Simplified Schematic

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