AD5263BRUZ200-R7 datasheet(21/28 Pages) AD

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Data Sheet

AD5263

Rev. F | Page 21 of 28

MULTIPLE DEVICES ON ONE BUS

Figure 49 shows four AD5263 devices on the same serial bus. Each

has a different slave address because the states of their AD0 and

AD1 pins are different. This allows each RDAC within each device

to be written to or read from independently. The master device

output bus line drivers are open-drain, pull-downs in a fully

I2C-compatible interface.

MASTER

AD5263

R P

+5V

SDA

SCL

AD0

AD1

SDA SCL

AD5263

AD0

AD1

SDA SCL

AD5263

AD0

AD1

SDA SCL

AD5263

AD0

AD1

SDA SCL

Figure 49. Multiple AD5263 Devices on One I2C Bus

LEVEL SHIFT FOR NEGATIVE VOLTAGE OPERATION

The digital potentiometer is popular in laser diode driver and

certain telecommunication equipment level-setting applications.

These applications are sometimes operated between ground and

some negative supply voltage so that the systems can be biased

at round to avoid large bypass capacitors that may significantly

impede the ac performance. Like most digital potentiometers, the

AD5263 can be configured with a negative supply (see Figure 50).

SDA

GND

VSS

VDD

SCL

LEVEL SHIFTED

–5V

AD5263

Figure 50. Biased at Negative Voltage

However, the digital inputs must also be level shifted to allow

proper operation because the ground is referenced to the negative

potential. As a result, Figure 51 shows one implementtation

with a couple of transistors and a few resistors. When VIN is

high, Q1 is turned on and its emitter is clamped at one threshold

above ground. This threshold appears at the base of Q2, which

causes Q2 to turn off. In this state, VOUT approaches −5 V. When

VIN is low, Q1 is turned off and the base of Q2 is pulled low, which

in turn causes Q2 to turn on. In this state, VOUT approaches 0 V.

Beware that proper time shifting is also needed for successful

communication with the device.

VIN

VOUT

–5V

2N3906

+5V

–5V

1kΩ

10kΩ

Figure 51. Level Shift for Bipolar Potential Operation

ESD PROTECTION

All digital inputs are protected with a series input resistor and

parallel Zener ESD structures shown in Figure 52 and Figure 53.

This protection applies to digital input pins SDI/SDA, CLK/SCL,

CS/AD0, RES/AD1, and SHDN.

LOGIC

340Ω

VSS

Figure 52. ESD Protection of Digital Pins

A,B,W

VSS

Figure 53. ESD Protection of Resistor Terminals

TERMINAL VOLTAGE OPERATING RANGE

The AD5263 positive VDD and negative VSS power supply defines

the boundary conditions for proper 3-terminal digital

potentiometer operation. Supply signals present on the A, B,

and W terminals that exceed VDD or VSS are clamped by the

internal forward-biased diodes shown in Figure 54.

VDD

VSS

Figure 54. Maximum Terminal Voltages Set by VDD and VSS

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at the A, B, and W terminals (see Figure 54), it is important to

power VDD and VSS before applying any voltage to the A, B, and

W terminals; otherwise, the diodes are forward biased such that

VDD and VSS are powered unintentionally and may affect the rest

of the circuit. The ideal power-up sequence is in the following

order: GND, VDD, VSS, VL, digital inputs, and VA/B/W. The relative

order of powering VA, VB, VW, and digital inputs is not important as

long as they are powered after VDD and VSS.

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