XPC855TCZP50D4 datasheet(8/76 Pages) MOTOROLA

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MPC860 Family Hardware Speciﬁcations

MOTOROLA

Power Dissipation

Part V Power Dissipation

Table 5-4 provides power dissipation information. The modes are 1:1, where CPU and bus

speeds are equal, and 2:1 mode, where CPU frequency is twice bus speed.

NOTE

Values in Table 5-4” represent VDDL-based power dissipation

and do not include I/O power dissipation over VDDH. I/O power

dissipation varies widely by application due to buffer current,

depending on external circuitry.

2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3 Per JEDEC JESD51-6 with the board horizontal.

4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate

method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed

pad packages where the pad would be expected to be soldered, junction to case thermal resistance is a simulated

value from the junction to the exposed pad without contact resistance.

6 Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

Table 5-4. Power Dissipation (PD)

Die Revision

Frequency (MHz)

Typical 1

1 Typical power dissipation is measured at 3.3 V.

Maximum 2

2 Maximum power dissipation is measured at 3.5 V.

Unit

A.3 and Previous

450

550

700

850

870

1050

B.1 and C.1

375

TBD

575

TBD

750

TBD

D.3 and D.4

(1:1 Mode)

656

735

TBD

D.3 and D.4

(2:1 Mode)

722

762

851

909

XPC855TCZP50D4 数据表(PDF) 8 Page - Motorola, Inc

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