AD8338

Data Sheet

Rev. 0 | Page 12 of 16

THEORY OF OPERATION

GETTING STARTED WITH THE AD8338

The AD8338 is a variable gain amplifier (VGA) that provides a

variable gain range of 80 dB. With a constant −3 dB bandwidth

of 18 MHz across all gains, a gain bandwidth product of 180 GHz

is achieved at the highest gain using only 4.5 mA of supply current.

The differential output allows the AD8338 to directly drive an

ADC input, simplifying board design and saving space and power.

In addition to its gain, bandwidth, and power performance, the

AD8338 includes a range of features that increase its versatility.

•

Single-supply operation ranging from 3.0 V to 5.0 V

•

Built-in offset correction circuit to cancel out dc offsets

•

Automatic gain control (AGC) circuit to control the gain

and keep the output at a steady rms level

Access to internal nodes at both the input and output allows the

user to adjust the gain range, adjust the output common-mode

voltage, and tune the bandwidth.

INPR and INMR Pins in the Standard Configuration

The gain is controlled by a user supplied voltage input applied to

the GAIN pin. The gain can be varied from 0 dB to 80 dB when

the default internal resistors are used; the voltage at the GAIN pin

can be varied from 0.1 V to 1.1 V. The default internal resistors

are used by applying the input voltage to the INPR and INMR

pins (Pin 1 and Pin 4; see Figure 39).

INPR

INPD

INMD

INMR

500Ω

500Ω

0dB TO 80dB

OUTP

OUTM

Figure 39. Input Voltage Applied to the INPR and INMR Pins

In the standard configuration, a differential input voltage applied

across INPR and INMR is amplified, with the output voltage

appearing differentially across OUTP and OUTM. The outputs

have a default common-mode voltage of VREF, which is equal

to 1.5 V.

GAIN and MODE Pins

The gain of the AD8338 is controlled by the GAIN and MODE

pins. Adjusting the voltage at the GAIN pin from 0.1 V to 1.1 V

adjusts the gain from its lowest to highest value.

The MODE pin controls the polarity of the gain adjustment. When

MODE is tied to VBAT, the gain of the AD8338 increases propor-

tionally with an increase of the voltage on the GAIN pin. When

MODE is tied to COMM, the gain decreases with an increase of

the voltage on the GAIN pin.

OFFSET CORRECTION CIRCUIT

The AD8338 provides an offset correction circuit to cancel out

any dc offsets that may be present. Connecting a 0.2 µF capacitor

from the OFSN pin to VREF allows frequencies above 400 Hz to

pass through, but eliminates dc offsets. For dc-coupled operation,

disable the offset correction circuit by connecting the OFSN pin

directly to the COMM pin. When the part is operated without

offset correction, exercise caution with large gains because any

offsets present large errors on the outputs.

Unlike a high-pass filter, the offset correction circuit allows signals

below the corner frequency to pass through with high levels of

crossover distortion. If a frequency below the band of interest may

present itself to the inputs, apply a filter in front of the VGA for

best performance.

unpredictable results. If the part is operated at frequencies below

400 Hz, disable the offset correction circuit and compensate the

offset externally.

The corner frequency can be approximately calculated as follows:

OFSN

C

C

f

×

×

π

=

600

2

1

(1)

EXPLANATION OF THE GAIN FUNCTION

From a designer’s standpoint, the gain of the AD8338 can be

modeled as three cascaded gain stages. The first stage can be

thought of as a differential input transconductance stage, where

the input current is proportional to the differential input voltage

that is applied to the input resistors, as follows:

N

P

IN

R

R

INMx

INPx

I

+

−

=

(2)

This current is then fed into the conceptual second stage, a

current input-current output VGA, which has a gain range

of −26 dB to +54 dB. The conceptual output current is given

by Equation 3.

(3)

greater than the input current.

The third and final stage can be modeled as a transimpedance

stage, expressed as follows:

(4a)

(4b)

(4c)