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SST12LP20 数据表(PDF) 12 Page - Microchip Technology |
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SST12LP20 数据表(HTML) 12 Page - Microchip Technology |
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12 / 13 page ![]() ©2013 Silicon Storage Technology, Inc. DS70005049C 05/13 12 2.4 GHz High-Efficiency, High-Gain Power Amplifier SST12LP20 Data Sheet Packaging Diagrams Figure 10:8-Contact Ultra-thin Small Outline No-lead (USON) SST Package Code: QUA TOP VIEW BOTTOM VIEW SIDE VIEW 0.60 0.50 0.08 Pin # 1 2.00 ±0.10 2.00 ±0.10 0.50 BSC 0.3 0.2 8-xson-2x2-QUA-2.0 1mm 0.05 Max 0.75 See notes 2 and 3 1.60 Note: 1. Similar to JEDEC JEP95 UQFN/USON variants, though number of contacts and some dimensions are different. 2. The topside pin #1 indicator is laser engraved; its approximate shape and location is as shown. 3. The external paddle is electrically connected to the die back-side and to VSS. This paddle must be soldered to the PC board; it is required to connect this paddle to the VSS of the unit. Connection of this paddle to any other voltage potential will result in shorts and electrical malfunction of the device. 4. Untoleranced dimensions are nominal target dimensions. 5. All linear dimensions are in millimeters (max/min). 1.55 Pin #1 (laser engraved see note 2) |
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