AD7621 datasheet(20/32 Pages) AD

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AD7621

Rev. 0 | Page 20 of 32

Power-Up

At power-up, or returning to operational mode from the power-

down mode (PD = high), the AD7621 engages an initialization

process. During this time, the first 128 conversions should be

ignored or the RESET input could be pulsed to engage a faster

initialization process. Refer to the Digital Interface section for

RESET and timing details.

A simple power-on reset circuit, as shown in Figure 23, can be

used to minimize the digital interface. As OVDD powers up, the

capacitor is shorted and brings RESET high; it is then charged

returning RESET to low. However, this circuit only works when

powering up the AD7621 because the power down mode (PD =

high) does not power down any of the supplies. As a result,

RESET is low.

POWER DISSIPATION VS. THROUGHPUT

In impulse mode, the AD7621 automatically reduces its power

consumption at the end of each conversion phase. During the

acquisition phase, the operating currents are very low which

allows a significant power saving when the conversion rate is

reduced (see Figure 30). This feature makes the AD7621 ideal

for very low power, battery-operated applications.

It should be noted that the digital interface remains active even

during the acquisition phase. To reduce the operating digital

supply currents even further, drive the digital inputs close to the

power rails (that is, OVDD and OGND).

SAMPLING RATE (SPS)

100

100k

10k

100

10k

100k

10M

WARP MODE POWER

IMPULSE MODE POWER

PDREF = PDBUF = HIGH

Figure 30. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

The AD7621 is controlled by the CNVST input. A falling edge

on CNVST is all that is necessary to initiate a conversion.

Detailed timing diagrams of the conversion process are shown

in Figure 31. Once initiated, it cannot be restarted or aborted,

even by the power-down input, PD, until the conversion is

complete. The CNVST signal operates independently of CS and

RD signals.

BUSY

MODE

CONVERT

ACQUIRE

CONVERT

CNVST

Figure 31. Basic Conversion Timing

For optimal performance, the rising edge of CNVST should not

occur after the maximum CNVST low time, t1, or until the end

of conversion.

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot, undershoot, or ringing.

The CNVST trace should be shielded with ground and a low

value (such as 50 Ω) serial resistor termination should be added

close to the output of the component that drives this line. Also,

a 60 pF capacitor is recommended to further reduce the effects

of overshoot and undershoot as shown in Figure 23.

For applications where SNR is critical, the CNVST signal should

have very low jitter. This can be achieved by using a dedicated

oscillator for CNVST generation, or by clocking CNVST with a

high frequency, low jitter clock, as shown in Figure 23.

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