AD8029AKSZ-R2 datasheet(16/24 Pages) AD

16 / 24 page

AD8029/AD8030/AD8040

Data Sheet

Rev. B | Page 16 of 24

THEORY OF OPERATION

03679-0-051

IN–

IN+

R5 R6 R7 R8

R1 R2

R3 R4

MTOP

ITAIL

MBOT

OUTPUT

BUFFER

–VS

RTH

ITH

+VS –1.2V

+VS

VOUT

Q10

Q11

CMT

CMB

–VS

AD8029 ONLY

TO DISABLE

CIRCUITRY

DISABLE

OUT

COM

SPD

Figure 50. Simplified Schematic

The AD8029 (single), AD8030 (dual), and AD8040 (quad) are

rail-to-rail input and output amplifiers fabricated using Analog

Devices’ XFCB process. The XFCB process enables the

AD8029/ AD8030/AD8040 to operate on 2.7 V to 12 V supplies

with a 120 MHz bandwidth and a 60 V/µs slew rate. A

simplified sche-matic of the AD8029/AD8030/AD8040 is

shown in Figure 50.

INPUT STAGE

For input common-mode voltages less than a set threshold

(1.2 V below VCC), the resistor degenerated PNP differential

pair (comprising Q1 toQ4) carries the entire ITAIL current,

allowing the input voltage to go 200 mV below –VS. Conversely,

input common-mode voltages exceeding the same threshold

cause ITAIL to be routed away from the PNP differential pair and

into the NPN differential pair through transistor Q9. Under this

condition, the input common-mode voltage is allowed to rise

200 mV above +VS while still maintaining linear amplifier

behavior. The transition between these two modes of operation

leads to a sudden, temporary shift in input stage transconduc-

tance, gm, and dc parameters (such as the input offset voltage

VOS), which in turn adversely affect the distortion performance.

The SPD block shortens the duration of this transition, thus

improving the distortion performance. As shown in Figure 50,

the input differential pair is protected by a pair of two series

diodes, connected in anti-parallel, which clamp the differential

input voltage to approximately ±1.5 V.

OUTPUT STAGE

The currents derived from the PNP and NPN input differential

pairs are injected into the current mirrors MBOT and MTOP, thus

establishing a common-mode signal voltage at the input of the

output buffer.

The output buffer performs three functions:

1. It buffers and applies the desired signal voltage to the

output devices, Q10 and Q11.

2. It senses the common-mode current level in the output

devices.

3. It regulates the output common-mode current by

establishing a common-mode feedback loop.

The output devices Q10 and Q11 work in a common-emitter

configuration, and are Miller-compensated by internal

capacitors, CMT and CMB.

The output voltage compliance is set by the output devices’

collector resistance RC (about 25 Ω), and by the required load

current IL. For instance, a light equivalent load (5 kΩ) allows the

output voltage to swing to within 40 mV of either rail, while

heavier loads cause this figure to deteriorate as RC × IL.

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