AD8029AKSZ-R2 datasheet(19/24 Pages) AD

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Data Sheet

AD8029/AD8030/AD8040

Rev. B | Page 19 of 24

CIRCUIT CONSIDERATIONS

PCB Layout

High speed op amps require careful attention to PCB layout to

achieve optimum performance. Particular care must be

exercised to minimize lead lengths of the bypass capacitors.

Excess lead inductance can influence the frequency response

and even cause high frequency oscillations. Using a multilayer

board with an internal ground plane can help reduce ground

noise and enable a more compact layout.

To achieve the shortest possible trace length at the inverting

input, the feedback resistor, RF, should be located the shortest

distance from the output pin to the input pin. The return node

of the resistor RG should be situated as close as possible to the

return node of the negative supply bypass capacitor.

On multilayer boards, all layers beneath the op amp should be

cleared of metal to avoid creating parasitic capacitive elements.

This is especially true at the summing junction, i.e., the inver-

ting input, –IN. Extra capacitance at the summing junction can

cause increased peaking in the frequency response and lower

phase margin.

Grounding

To minimize parasitic inductances and ground loops in high

speed, densely populated boards, a ground plane layer is critical.

Understanding where the current flows in a circuit is critical in

the implementation of high speed circuit design. The length of

the current path is directly proportional to the magnitude of the

parasitic inductances and thus the high frequency impedance of

the path. Fast current changes in an inductive ground return

will create unwanted noise and ringing.

The length of the high frequency bypass capacitor pads and

traces is critical. A parasitic inductance in the bypass grounding

works against the low impedance created by the bypass

capacitor. Because load currents flow from supplies as well as

from ground, the load should be placed at the same physical

location as the bypass capacitor ground. For large values of

capacitors, which are intended to be effective at lower

frequencies, the current return path length is less critical.

Power Supply Bypassing

Power supply pins are actually inputs to the op amp. Care must

be taken to provide the op amp with a clean, low noise dc

voltage source.

Power supply bypassing is employed to provide a low imped-

ance path to ground for noise and undesired signals at all

frequencies. This cannot be achieved with a single capacitor

type; but with a variety of capacitors in parallel the bandwidth

of power supply bypassing can be greatly extended. The bypass

capacitors have two functions:

1. Provide a low impedance path for noise and undesired

signals from the supply pins to ground.

2. Provide local stored charge for fast switching conditions

and minimize the voltage drop at the supply pins during

transients. This is typically achieved with large electrolytic

capacitors.

Good quality ceramic chip capacitors should be used and

always kept as close as possible to the amplifier package. A

parallel combination of a 0.1 µF ceramic and a 10 µF electrolytic

covers a wide range of rejection for unwanted noise. The 10 µF

capacitor is less critical for high frequency bypassing and, in

most cases, one per supply line is sufficient. The values of

capacitors are circuit-dependant and should be determined by

the system’s requirements.

DESIGN TOOLS AND TECHNICAL SUPPORT

Analog Devices is committed to the design process by providing

technical support and online design tools. ADI offers technical

support via free evaluation boards, sample ICs, Spice models,

interactive evaluation tools, application notes, phone and email

support—all available at www.analog.com.

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