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AD9268 数据表(PDF) 7 Page - Analog Devices |
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AD9268 数据表(HTML) 7 Page - Analog Devices |
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7 / 44 page  AD9268 Rev. A | Page 7 of 44 AD9268BCPZ-80 AD9268BCPZ-105 AD9268BCPZ-125 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit WORST OTHER (HARMONIC OR SPUR) Without Dither fIN = 2.4 MHz 25°C −99 −100 −100 dBc fIN = 70 MHz 25°C −100 −96 −99 −94 −100 −94 dBc Full −96 −94 −94 dBc fIN = 140 MHz 25°C −98 −98 −98 dBc fIN = 200 MHz 25°C −96 −94 −96 dBc With On-Chip Dither fIN = 2.4 MHz 25°C −108 −107 −108 dBc fIN = 70 MHz 25°C −106 −96 −107 −95 −106 −95 dBc Full −96 −95 −95 dBc fIN = 140 MHz 25°C −105 −104 −103 dBc fIN = 200 MHz 25°C −102 −102 −99 dBc TWO-TONE SFDR, WITHOUT DITHER fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS) 25°C 93 92 90 dBc fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS) 25°C 81 80 82 dBc CROSSTALK2 Full −95 −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. Parameter Temperature Min Typ Max Unit DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ SYNC INPUT Logic Compliance CMOS Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V High Level Input Voltage Full 1.2 AVDD V Low Level Input Voltage Full AGND 0.6 V High Level Input Current Full −100 +100 μA Low Level Input Current Full −100 +100 μA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ |
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