ADP2302ARDZ-3.3-R7 datasheet(14/28 Pages) AD

14 / 28 page

ADP2302/ADP2303

Data Sheet

Rev. A | Page 14 of 28

THEORY OF OPERATION

The ADP2302/ADP2303 are nonsynchronous, step-down,

dc-to-dc regulators, each with an integrated high-side power

MOSFET. The high switching frequency and 8-lead SOIC

package provide a small, step-down, dc-to-dc regulator

solution.

The ADP2302/ADP2303 can operate with an input voltage from

3.0 V to 20 V while regulating an output voltage down to 0.8 V.

The ADP2302 can provide 2 A maximum continuous output

current, and the ADP2303 can provide 3 A maximum

continuous output current.

BASIC OPERATION

The ADP2302/ADP2303 use the fixed-frequency, peak current-

mode PWM control architecture from medium to high loads,

but shift to a pulse-skip mode control scheme at light loads to

reduce the switching power losses and improve efficiency. When

these devices operate in fixed-frequency PWM mode, output

regulation is achieved by controlling the duty cycle of the integrated

MOSFET. While the devices are operating in pulse-skip mode at

light loads, the output voltage is controlled in a hysteretic

manner with higher output ripple. In this mode of operation, the

regulator periodically stops switching for a few cycles, thus

keeping the conversion losses minimal to improve efficiency.

PWM MODE

In PWM mode, the ADP2302/ADP2303 operate at a fixed

frequency, set by an internal oscillator. At the start of each

oscillator cycle, the MOSFET switch is turned on, providing a

positive voltage across the inductor. The inductor current

increases until the current-sense signal crosses the peak

inductor current threshold that turns off the MOSFET switch;

this threshold is set by the error amplifier output. During the

MOSFET off time, the inductor current declines through the

external diode until the next oscillator clock pulse comes and a

new cycle starts.

POWER SAVING MODE

To achieve higher efficiency, the ADP2302/ADP2303 smoothly

transition to the pulse-skip mode when the output load decreases

below the pulse-skip current threshold. When the output vol-

tage dips below the regulation, the ADP2302/ADP2303 enter

PWM mode for a few oscillator cycles until the voltage increases

to regulation range. During the idle time between bursts, the

MOSFET switch is turned off, and the output capacitor supplies

all the output current.

Because the pulse-skip mode comparator monitors the internal

compensation node, which represents the peak inductor current

information, the average pulse-skip load current threshold

depends on the input voltage (VIN), the output voltage (VOUT),

the inductor, and the output capacitor.

Because the output voltage occasionally dips below regulation

and then recovers, the output voltage ripple in the power saving

mode is larger than the ripple in the PWM mode of operation.

BOOTSTRAP CIRCUITRY

The ADP2302/ADP2303 each have an integrated boot regulator,

which requires that a 0.1 μF ceramic capacitor (X5R or X7R) be

placed between the BST and SW pins to provide the gate drive

voltage for the high-side MOSFET. There is at least a 1.2 V

difference between the BST and SW pins to turn on the high-side

MOSFET. This voltage should not exceed 5.5 V in case the BST

pin is supplied with the external voltage source through a diode.

The ADP2302/ADP2303 generate a typical 5.0 V bootstrap voltage

for the gate drive circuit by differentially sensing and regulating

the voltage between the BST and SW pins. There is a diode

integrated on the chip that blocks the reverse voltage between the

VIN and BST pins when the MOSFET switch is turned on.

PRECISION ENABLE

The ADP2302/ADP2303 provide a precision enable circuit that

has 1.2 V reference threshold with 100 mV hysteresis. When the

voltage at the EN pin is greater than 1.2 V (typical), the part is

enabled. If the EN voltage falls below 1.1 V (typical), the chip

is disabled. The precision enable threshold voltage allows the

ADP2302/ADP2303 to be easily sequenced from other input/

output supplies. It also can be used as a programmable UVLO

input by using a resistive divider. An internal 1.2 μA pull-down

current prevents errors if the EN pin is left floating.

INTEGRATED SOFT START

The ADP2302/ADP2303 have an internal digital soft start

circuitry to limit the output voltage rise time and reduce

the inrush current at power up. The soft start time is fixed at

2048 clock cycles.

CURRENT LIMIT

The ADP2302/ADP2303 include current-limit protection circuitry

to limit the amount of positive current flowing through the high-

side MOSFET switch. The positive current limit on the power

switch limits the amount of current that can flow from the input

to the output.

SHORT-CIRCUIT PROTECTION

The ADP2302/ADP2303 include frequency foldback to prevent

output current runaway when there is a hard short on the output.

The switching frequency is reduced when the voltage at the FB pin

drops below a certain value, which allows more time for the

inductor current to decline, but increases the ripple current while

regulating the peak current. This results in a reduction in average

output current and prevents output current runaway. The corre-

lation between the switching frequency and the FB pin voltage

is shown in Table 5.

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