AD8657

Rev. A | Page 17 of 24

APPLICATIONS INFORMATION

The AD8657 is a low power, rail-to-rail input and output

precision CMOS amplifier that operates over a wide supply

voltage range of 2.7 V to 18 V. This amplifier uses the Analog

Devices DigiTrim technique to achieve a higher degree of

precision than is available from other CMOS amplifiers. The

DigiTrim technique is a method of trimming the offset voltage

of an amplifier after assembly. The advantage of postpackage

trimming is that it corrects any shifts in offset voltage caused by

mechanical stresses of assembly.

The AD8657 also employs unique input and output stages to

achieve a rail-to-rail input and output range with a very low

supply current.

INPUT STAGE

Figure 63 shows the simplified schematic of the AD8657. The

input stage comprises two differential transistor pairs, an NMOS

pair (M1, M2) and a PMOS pair (M3, M4). The input common-

mode voltage determines which differential pair turns on and is

more active than the other.

The PMOS differential pair is active when the input voltage

approaches and reaches the lower supply rail. The NMOS pair

is needed for input voltages up to and including the upper supply

rail. This topology allows the amplifier to maintain a wide

dynamic input voltage range and to maximize signal swing to

both supply rails.

For the majority of the input common-mode voltage range, the

PMOS differential pair is active. Differential pairs commonly

exhibit different offset voltages. The handoff from one pair to the

to-rail amplifiers that use the dual differential pair topology.

Therefore, always choose a common-mode voltage that does not

include the region of handoff from one input differential pair to

the other.

input common-mode voltage approaches the power supply rails.

These changes are a result of the load transistors (M8, M9, M14,

and M15) running out of headroom. As the load transistors are

forced into the triode region of operation, the mismatch of their

drain impedances contributes to the offset voltage of the amplifier.

This problem is exacerbated at high temperatures due to the

decrease in the threshold voltage of the input transistors (see

Figure 9, Figure 10, Figure 12, and Figure 13 for typical perfor-

mance data).

Current Source I1 drives the PMOS transistor pair. As the input

common-mode voltage approaches the upper rail, I1 is steered

away from the PMOS differential pair through the M5 transistor.

The bias voltage, VB1, controls the point where this transfer occurs.

M5 diverts the tail current into a current mirror consisting of the

M6 and M7 transistors. The output of the current mirror then

drives the NMOS pair. Note that the activation of this current

mirror causes a slight increase in supply current at high common-

mode voltages (see Figure 23 and Figure 26 for more details).

The AD8657 achieves its high performance by using low voltage

MOS devices for its differential inputs. These low voltage MOS

devices offer excellent noise and bandwidth per unit of current.

Each differential input pair is protected by proprietary regulation

circuitry (not shown in the simplified schematic). The regula-

tion circuitry consists of a combination of active devices that

maintain the proper voltages across the input pairs during normal

operation and passive clamping devices that protect the amplifier

during fast transients. However, these passive clamping devices

begin to forward bias as the common-mode voltage approaches

either power supply rail. This causes an increase in the input

bias current (see Figure 15 and Figure 18).

The input devices are also protected from large differential

input voltages by clamp diodes (D1 and D2). These diodes are

buffered from the inputs with two 10 kΩ resistors (R1 and R2).

The differential diodes turn on whenever the differential voltage

exceeds approximately 600 mV; in this condition, the differential

input resistance drops to 20 kΩ.

OUTPUT STAGE

The AD8657 features a complementary output stage consisting

of the M16 and M17 transistors. These transistors are configured

in Class AB topology and are biased by the voltage source, VB2.

This topology allows the output voltage to go within millivolts

of the supply rails, achieving a rail-to-rail output swing. The output

voltage is limited by the output impedance of the transistors, which

of the load current and can be estimated using the output voltage to

the supply rail vs. load current diagrams (see Figure 16, Figure 17,

Figure 19, and Figure 20).