LAN8720AI datasheet(72/79 Pages) SMSC

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Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

Datasheet

Revision 1.4 (08-23-12)

SMSC LAN8720A/LAN8720Ai

DATASHEET

5.5.4.2

RMII Timing (REF_CLK In Mode)

The 50MHz REF_CLK IN timing applies to the case when nINTSEL is floated or pulled-high. In this

mode, a 50MHz clock must be input on the CLKIN pin. For more information on REF_CLK In Mode,

see Section 3.7.4.1, "REF_CLK In Mode," on page 34.

Note 5.17 Timing was designed for system load between 10 pf and 25 pf.

Figure 5.5 RMII Timing (REF_CLK In Mode)

Table 5.10 RMII Timing Values (REF_CLK In Mode)

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

NOTES

tclkp

CLKIN period

tclkh

CLKIN high time

tclkp*0.35

tclkp*0.65

tclkl

CLKIN low time

tclkp*0.35

tclkp*0.65

toval

RXD[1:0], RXER, CRS_DV output valid from

rising edge of CLKIN

14.0

Note 5.17

tohold

RXD[1:0], RXER, CRS_DV output hold from

rising edge of CLKIN

3.0

Note 5.17

tsu

TXD[1:0], TXEN setup time to rising edge of

CLKIN

4.0

Note 5.17

tihold

TXD[1:0], TXEN input hold time after rising edge

of CLKIN

1.5

Note 5.17

CLKIN

(REF_CLK)

RXD[1:0],

RXER

CRS_DV

tclkh

tclkl

tclkp

toval

tohold

toval

tohold

tsu

TXD[1:0]

TXEN

tihold

tsu tihold

tihold

tsu

tihold

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