Z8023016PSG datasheet(13/118 Pages) ZILOG

13 / 118 page

PS005308-0609

Functional Description

Z80230/Z85230/L

Product Specification

Functional Description

The architecture of the ESCC is described based on its functionality as a:

• Data communications device, which transmits and receives data in a wide variety of

protocols

• Microprocessor peripheral, in which the ESCC offers valuable features such as

vectored interrupts and DMA support

The details of the communication between the receive and transmit logic of the system bus

are displayed in Figure 5 and Figure 6 on page 9. The features and data path for each of

the ESCC A and B channels are identical. For more information on SCC/ESCC and ISCC

Family of Products, refer to the respective User Manuals available for download from

www.zilog.com.

Figure 5. ESCC Transmit Data Path

WR7

WR6

SYNC Register

20-Bit TX

Shift Register

Zero Insert

CRC-SDLC

CRC-Gen

From Receiver

SYNC Register

Internal Data Bus

WR8

TX FIFO

Internal TXD

ASYNC

SYNC

SDLC

Transmit Clock

Final Tx

MUX

NRZI Encode

Transmit

MUX and

2 Bit Delay

TXD

to Other Channel

4 Bytes

Z8023016PSG 数据表(PDF) 13 Page - Zilog, Inc.

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