Z8023016PSG datasheet(21/118 Pages) ZILOG

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PS005308-0609

Functional Description

Z80230/Z85230/L

Product Specification

ASYNCHRONOUS Mode

The ESCC has significant improvements over the standard Serial Communications Con-

troller (SCC). The addition of the deeper data FIFOs provide greater protection against

underruns and overruns as well as more efficient use of bus bandwidth. The deeper data

FIFOs are accessible regardless of the protocol used and they need not be enabled. For

information on these improvements, see Z80230/Z85230/L Enhancements on page 22

Send and Receive allow 5 to 8 bits per character, plus optional Even or Odd parity. The

transmitters can supply 1, 1.5, or 2 stop bits per character and can provide break indica-

tion. The receiver break-detection logic interrupts the CPU both at the start and at the end

of a received break. Reception is protected from spikes by start-bit validation that delays

the signal for a length of time equal to one half the time period required to process 1 bit of

data after a Low level is detected on the receive data input (RxDA or RxDB pins). If the

Low level does not persist (that is, a transient), the character assembly process does not

start.

Framing errors and overrun errors are detected and buffered together with the character at

which they occur. Vectored interrupts allow fast servicing of error conditions. Further-

more, a built-in checking process avoids the interpretation of a framing error as a new start

bit. A framing error results in the addition of a delay of one half the amount of time

required to process 1 bit of data at the point at which the search for the next start bit

begins. Transmit and Receive clock can be selected from any of the several sources. In

ASYNCHRONOUS mode, the SYNC pin may be programmed as an input with interrupt

capability.

SYNCHRONOUS Mode

The ESCC supports both byte-oriented and bit-oriented SYNCHRONOUS communica-

tion. SYNCHRONOUS byte-oriented protocols are handled in several modes. They

enable character synchronization with a 6- or 8-bit SYNC character (MONOSYNC) or a

12-bit or 16-bit synchronization pattern (BISYNC), or with an external sync signal. Lead-

ing sync characters are removed without interrupting the CPU.

5- or 7-bit sync characters are detected from 8- or 16-bit patterns in the ESCC by overlap-

ping the larger pattern across multiple incoming sync characters as displayed in Figure 9.

Figure 9. Detecting 5- or 7-Bit Synchronous Characters

SYNC

Data

SYNC

Data

5 Bits

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