DS92001

SNLS147F – JUNE 2002 – REVISED APRIL 2013

www.ti.com

Figure 8. TRI-STATE Delay Test Circuit

Figure 9. Output active to TRI-STATE and TRI-STATE to active output time

PIN DESCRIPTIONS

Input/Outp

Pin Name

Pin #

Description

ut

GND

1

P

Ground

IN

−

2

I

Inverting receiver B/LVDS input pin

IN+

3

I

Non-inverting receiver B/LVDS input pin

N/C

4

NA

"NO CONNECT" pin

5

P

Power Supply, 3.3V ± 0.3V.

OUT+

6

O

Non-inverting driver BLVDS output pin

OUT -

7

O

Inverting driver BLVDS output pin

EN

8

I

Enable pin. When EN is LOW, the driver is disabled and the BLVDS outputs

are in TRI-STATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL

levels.

GND

DAP

P

WSON Package Ground

6

Submit Documentation Feedback

Copyright © 2002–2013, Texas Instruments Incorporated

Product Folder Links: DS92001