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MC68331TS 数据表(PDF) 33 Page - Freescale Semiconductor, Inc |
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MC68331TS 数据表(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 84 page  MC68331TS/D 33 R/W —Read/Write This field causes a chip select to be asserted only for a read, only for a write, or for both read and write. Refer to the following table for options available. STRB —Address Strobe/Data Strobe 0 = Address strobe 1 = Data strobe This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address strobe causes chip select to be asserted synchronized with address strobe. Selecting data strobe caus- es chip select to be asserted synchronized with data strobe. DSACK —Data and Size Acknowledge This field specifies the source of DSACK in asynchronous mode. It also allows the user to adjust bus timing with internal DSACK generation by controlling the number of wait states that are inserted to op- timize bus speed in a particular application. The following table shows the DSACK field encoding. The fast termination encoding (1110) is used for two-cycle access to external memory. Byte Description 00 Disable 01 Lower Byte 10 Upper Byte 11 Both Bytes R/W Description 00 Reserved 01 Read Only 10 Write Only 11 Read/Write DSACK Description 0000 No Wait States 0001 1 Wait State 0010 2 Wait States 0011 3 Wait States 0100 4 Wait States 0101 5 Wait States 0110 6 Wait States 0111 7 Wait States 1000 8 Wait States 1001 9 Wait States 1010 10 Wait States 1011 11 Wait States 1100 12 Wait States 1101 13 Wait States 1110 Fast Termination 1111 External DSACK Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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